Design Flow Manager

Overview

A typical design path includes the design entry phase, synthesis, and implementation (fitting and Place&Route processing). Each stage is typically followed by simulation. Active-HDL�s Design Flow Manager is designed to automate these processes. The main functions of this tool are:

• Handling bi-directional communication between the Active-HDL environment and external third-party tools used for C/HDL synthesis and implementation

• Version/Revision control; the Design Flow Manager compares dates of the design files and library units modification at all stages of the design processing to make sure that all changes introduced into source files propagate through the entire design path

• Providing a graphical user interface that allows controlling external third-party C/HDL/physical synthesis and implementation tools from the Active-HDL environment and specify user-defined tool-specific settings for individual design processes. This goal is achieved by means of design flowcharts or dedicated Tcl scripts (or sets of scripts) generated by the Design Flow Manager.

• Running C, HDL, or physical synthesis and implementation tools in the GUI or batch mode

• Initializing and running functional, post-synthesis, and timing simulation

• Collaboration with Server Farm, which allows designers to put in the queue their simulation, synthesis, and implementation tasks

• Getting results of finished jobs scheduled in the Design Flow Manager

• Running the Design Verification Manager (DVM)

• Initializing a debugging session of your embedded system by using CoVer

• Launching Additional Flow Tools

The user interface of the Design Flow Manager takes the form of design flowcharts. Active-HDL provides a number of design flowcharts for a variety of vendors. Depending on a target PLD device set for the current design (in the Flow Configuration Settings dialog box), the Design Flow Manager displays the appropriate flowchart in the Design Flow window.

The flowcharts may differ and provide different sets of options and buttons. For more information about individual flowchart options, click the related button in the Design Flow Manager window presented below:

NOTE: The RTL schematic/Technology schematic button runs an external third-party graphical tool that allows you to visualize synthesis results in the form of an RTL schematic. The Design Flow Manager enables this feature only for selected synthesis tools. Refer to the Precision RTL, Synplify/Synplify Pro, Synplicity Synplify Pro with Amplify, and XST synthesis options, respectively.

The design flowchart:

• Shows the design path in a graphical form

• Provides buttons invoking applications used to process the design

• Allows running a C/HDL/physical synthesis and implementation process in the GUI or batch mode by using scripts

• Allows generating synthesis, implementation, and simulation scripts on the basis of the current settings

• Allows easy access to log and report files generated by synthesis and implementation tools

• Displays synthesis and implementation status information

• Provides access to synthesis, implementation, and simulation options

• Provides access to additional flow tools provided by EDA vendors

• Allows executing the simulation, synthesis, or implementation process that will start on a remote computer of Server Farm

• Allows downloading all or selected resulting files created during the simulation, synthesis, or implementation process executed on a remote computer of Server Farm

• Allows starting the Design Verification Manager and running a hardware embedded simulation (HES)

• Allows starting CoVer and debugging an embedded system

Design flowcharts are configurable and can be flexibly adjusted to available tools and required options. The Flow Configuration Settings dialog box allows users to set among others:

• Vendor, family, and type of a target device

• C/HDL/physical synthesis and/or implementation tool

• Location of a tool's executable file

• Whether the simulation, synthesis, or implementation process should be executed locally or on Server Farm

• Farm Controller for a synthesis, implementation, or simulation task that will be run on Server Farm

The flowchart configuration determines the number and layout of the flowchart buttons. Some implementation tools perform synthesis and implementation as a single process. For such tools, the flowchart does not provide separate buttons for synthesis and post-synthesis simulation.

Flowchart Status Information

The design flowchart shows flags next to the synthesis and implementation buttons that indicate the overall status of the synthesis and implementation processes. Their meaning is as follows: