The following is a brief overview of new features and changes available in the update for the Design Flow Manager of Active-HDL 7.2.SP2 (BUILD 1643.SP2.21, 06/27/2007): 

Design Flow Manager

�   New flowcharts

HDL Synthesis
1. Synplicity Synplify 8.8 for Actel (incl. Synplicity Synplify 8.8A1)
2. Synplicity Synplify/Synplify Pro/Synplify Premier 8.9
3. Xilinx XST 9.2 VHDL/Verilog (incl. Service Pack 2)

Implementation
1. Actel Designer 8.0 (incl. Service Pack 1)
2. QuickLogic QuickWorks 9.9
3. Xilinx ISE/WebPack 9.2 (incl. Service Pack 2)

�   Updated flowcharts

Implementation
1. Altera Quartus II 7.1 (incl. Service Pack 1)

�   Flowchart Changes

Cypress flowchart
1. The Cypress Warp flowchart has been removed.

Xilinx flowchart
2. The Xilinx Triscend FastChip flowchart has been removed.

The Update for Design Flow Manager is available at: http://support.aldec.com/UpdateCenter/File.aspx?fid=00000645