The HES-XCVU9P-QDR board with Xilinx Virtex UltraScale+ XCVU9P FPGA enables High Performance Computing (HPC) solutions with a need for high-bandwidth and low-latency communication through QSFP28. The customizable FPGA combined with QDR-II+ or DDR4 memory modules provides high throughput for software acceleration, data processing, telecommunications, and more. The PCIe x16 half-length low-profile board easily fits into enterprise rack systems for maximum performance density.
The board is available in two memory configurations:
Main FPGA Resources |
|
XCVU9P |
|
Logic Cells |
2,586,150 |
Total Block RAM (Mb) |
75.9 |
UltraRAM (Mb) |
270 |
DSP Slices |
6,840 |
There are four (4) general-purpose clocks (100MHz, 200MHz, 300MHz, and 400MHz) available to the FPGA, three (3) dedicated clock oscillators with buffers for the QDR-II memory, a dedicated clock generator for the PCIe interface, and up to two (2) i2c programmable oscillators for the QSFP28 interfaces. Clock distribution and routing has been designed to assure a high level of signal integrity.
A standard connection is established with a workstation or server through the board's PCIe x16 interface. Aldec provides the Hes.Asic.Proto software package with necessary drivers and utilities for programming and communication with the board. Power is supplied by a standard 6-pin PCIe power cable. Several i2c devices are also available, including two EEPROM memories, a temperature sensor, and a current monitor which all share the i2c bus. Each QSFP28 cage supports 100Gb Ethernet connections for high-speed communication.
FPGA & Capacity
Memory Resources
Flexible Clocking
Interfaces & Hosting: