FPGA Design Creation and FPGA Simulation
Active-HDL™ is a Windows® based, integrated FPGA design creation and simulation solution for team-based environments. Active-HDL’s integrated design environment (IDE) includes a full HDL and graphical design tool suite and RTL/gate-level mixed-language simulator for rapid deployment and verification of FPGA designs.
The design flow manager evokes 200+ EDA and FPGA tools, during design entry, simulation, synthesis and implementation flows and allows teams to remain within one common platform during the entire FPGA development process. Active-HDL supports industry leading FPGA devices from AMD, Intel, Lattice, Microchip, Quicklogic and more.
Top Features and Benefits
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Unified Team-based Design Management maintains uniformity across local or remote teams
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Configurable FPGA/EDA Flow Manager interfaces with 200+ vendors tools allows teams to remain on one platform throughout FPGA development
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Quickly deploy designs by using Text, Schematic and State Machine
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Distribute or deliver IPs using more secure and reliable Interoperable Encryption standard
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Powerful common kernel mixed language simulator that supports VHDL, Verilog, SystemVerilog and SystemC
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Ensure code quality and reliability using graphically interactive debugging and code quality tools
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Perform metrics driven verification to identify unexercised parts of your design using Code Coverage analysis tools
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Improve verification quality and find more bugs using ABV - Assertion-Based Verification (SVA, PSL)
- Ability to simulate advanced verification constructs like SV Functional Coverage, Constrained Randomization and UVM
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Connect the gap between HDL simulation and high level mathematical modeling environment for DSP blocks using MATLAB®/Simulink® interface
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Abstract design intelligence and represent them in easy to understand graphical form using HDL to schematic converter
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Share designs quickly with auto-generate Design Documentation in HTML and PDF
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Tel: +1 702 990 4400
Fax: +1 702 990 4414
https://www.aldec.com
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