Free Active-HDL Student Edition
Active-HDL Student Edition is a mixed language design entry and simulation tool offered at no cost by Aldec for students to use during their course work.
Active-HDL Student Edition includes a "load and go" license. This means students can begin using it immediately after installing.
Key Features of Active-HDL Student Edition
- Mixed language simulator
- Multi-FPGA & EDA Tool Design Flow Manager
- Graphical Design entry & editing
- Code2Graphics and Graphics2Code
- Pre-compiled FPGA vendor libraries
- IEEE Language Support: VHDL2008, Verilog®, SystemVerilog(Design), SystemC
- Accelerated Waveform Viewer and List Viewer
- Interface with MATLAB®/Simulink®
- HTML and PDF Design Documentation
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Fax: +1 702 990 4414
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Printed version of site: support.aldec.com/en/products/fpga_simulation/active_hdl_student