Riviera-PRO™ addresses verification needs of engineers crafting tomorrow’s cutting-edge FPGA and SoC devices. Riviera-PRO enables the ultimate testbench productivity, reusability, and automation by combining the high-performance simulation engine, advanced debugging capabilities at different levels of abstraction, and support for the latest Language and Verification Library Standards.
Top Features and Benefits
High Performance Simulation
Extensive simulation optimization algorithms to achieve the highest performance in VHDL, Verilog/SystemVerilog, SystemC, and mixed-language simulations
The industry-leading capacity and simulation performance enable high regression throughput for developing the most complex systems
Support for the latest Verification Libraries, including Universal Verification Methodology (UVM)
Support for VHDL verification libraries, including OSVVM and UVVM.