FPGA Test System

DO-254/CTS™ is a fully customized hardware and software platform that augments target board testing to increase verification coverage by test and satisfy the verification objectives of DO-254/ED-80. The target design runs at-speed in the target device mounted on the custom daughter board. The simulation testbench is used as test vectors to enable requirements-based testing with 100% FPGA pin-level controllability and visibility necessary to implement normal range and abnormal range tests. The FPGA testing results are captured at-speed and displayed using a simulator waveform viewer for advanced analysis and documentation.

Top Features

  • At-speed testing in target device
  • Reuse testbench as test vectors
  • Increase verification coverage by test
  • FPGA I/Os full visibility/controllability
  • Early access to FPGA hardware board for device testing
  • For use with Altera®, Lattice®, Mircrosemi® and Xilinx® devices
  • Supports FPGAs with serial high speed I/Os (ARINC 818, PCIe, DDR3 and LVDS)
  • Single environment to verify all FPGA level requirements
  • Automated in-hardware testing
  • Hardware testing results visualization with waveform viewer
  • Integration with 3rd Party RTL Simulator, Synthesis and P&R Tools

CTS Flow
DO-254/CTS Flow, do 254 training, do254 training, do-254 training

Mother Board
DO-254/CTS Mother Board, do 254 training, do254 training, do-254 training

Daughter Board
DO-254/CTS Daughter Board, do 254 training, do254 training, do-254 training
Printed version of site: support.aldec.com/en/products/mil_aero_verification/do-254