ALINT-EDU Configurations

The integrated debugging environment allows system level designers to run mixed simulation based on SystemC and HDL code from a common design environment. More >>

The Phase-Based Linting methodology significantly improves user productivity and overall efficiency of the entire linting process. The PBL puts clear priorities into the design analysis process by reducing the total number of issues to deal with and minimizing the number of design refinement iterations. It speeds up debugging time by 3-10X compared to the traditional approach. More >>

ALINT-PRO™ enables project task management based on the Tasks window. The window is an easy to use tool which represents current list of tasks assigned within a project.More >>

ALDEC simulators provide full support of the IEEE 1364-2005 Standard. To enable simulation of a large variety of Verilog designs, both legacy and new, ALDEC simulators can be set to work in Verilog ’95, 2001 and 2005 modes.More >>

ALDEC simulators provide comprehensive support of the IEEE 1076-1993 Standard, IEEE 1076™-2002 VHDL standard and majority of just published IEEE 1076™-2008 Standard.More >>

Configuration ViewerMore >>

Quick Launch PanelMore >>

Rule Description ViewerMore >>

Rule Plug-in ViewerMore >>

ALINT allows to cross-probe the violations to their source. More >>

The Violation Viewer provides the convenient way of managing the results of the linting session.More >>

The network floating configuration (multiple users) is based on a license started on a remote machine (license server) running on the Windows or Linux platform.More >>

Linux x86/x86_64 support.More >>

Builds are tested on all the latest platforms, including Windows 8, to ensure correct operation on users' workstations.More >>