Universal Verification Methodology (UVM)

UVM has been the de-facto verification methodology for ASIC designs for at least a decade, and it’s now becoming popular for high-density and high-reliability FPGA and SoC FPGA designs. UVM was originally created by Accellera in 2011, and in 2020 it became an IEEE standard as IEEE 1800.2-2020. UVM is an open-source library written in SystemVerilog, and it utilizes the power of object-oriented programming for hardware designs.

 

With a set of APIs that defines a base class library for developing scalable, modular, and reusable verification components, UVM aims to make the verification process more flexible by enabling users to assemble powerful test environments using constrained random stimulus generation and functional coverage methodologies.

 

Aldec’s tools support compilation and simulation of UVM, and the latest UVM library is included in the installation of the latest versions of Active-HDL and Riviera-PRO. Riviera-PRO provides UVM-specific features such as an automatic UVM testbench generator, a UVM RAL generator and a UVM Viewer (Graph, Hierarchy and Configuration Windows).

 

Primary Use Case

UVM supports designs in VHDL, Verilog or SystemVerilog and is ideal for large teams working on ASIC, large FPGA and SoC FPGA projects. UVM improves interoperability, reduces the cost of reusing IPs with new projects, and makes it easier to reuse verification components from block-level to system-level. Overall, adopting this standard will lower verification costs and improve design quality.

 

Benefits

UVM is a standardized methodology that defines several best practices in verification to maximize reusability.

 

 

Webinar Video: Don't Be Afraid of UVM (UVM for Hardware Designers)

Hardware Designers are usually very busy doing their work and have little time left for experimentation with new methodologies. Unfortunately for them, official documentation of UVM (Universal Verification Methodology) was written by Verification Engineers for Verification Engineers, concentrating on high-level features, and completely neglecting lower-level details such as connecting UVM testbench to your design. Our webinar starts with a solid review of SystemVerilog interfaces with special attention paid to Virtual Interfaces. Then it proceeds to Sequences and other Data Items, processed by Sequencers and fed to the design under test via Drivers. The role of Monitors and Scoreboards in analysis of results is explained. The presentation concludes with environment configuration and running tests from the top-level module.

 

 

Other Webinar Recordings for UVM

 

Additional Links



Printed version of site: support.aldec.com/en/solutions/functional_verification/uvm_ovm_vmm--emulators-and-debuggers-in-embedded-system