Universal Verification Methodology (UVM)

UVM has been the de-facto verification methodology for ASIC designs for at least a decade, and it’s now becoming popular for high-density and high-reliability FPGA and SoC FPGA designs. UVM was originally created by Accellera in 2011, and in 2020 it became an IEEE standard as IEEE 1800.2-2020. UVM is an open-source library written in SystemVerilog, and it utilizes the power of object-oriented programming for hardware designs.

With a set of APIs that defines a base class library for developing scalable, modular, and reusable verification components, UVM aims to make the verification process more flexible by enabling users to assemble powerful test environments using constrained random stimulus generation and functional coverage methodologies.

Aldec’s tools support compilation and simulation of UVM, and the latest UVM library is included in the installation of the latest versions of Active-HDL and Riviera-PRO. Riviera-PRO provides UVM-specific features such as an automatic UVM testbench generator, a UVM RAL generator and a UVM Viewer (Graph, Hierarchy and Configuration Windows).

Primary Use Case

UVM supports designs in VHDL, Verilog or SystemVerilog and is ideal for large teams working on ASIC, large FPGA and SoC FPGA projects. UVM improves interoperability, reduces the cost of reusing IPs with new projects, and makes it easier to reuse verification components from block-level to system-level. Overall, adopting this standard will lower verification costs and improve design quality.

Benefits

UVM is a standardized methodology that defines several best practices in verification to maximize reusability.

Object Oriented Programming and Class Reference. This library consists of classes, utilities, and macros that are divided into the following categories: Base, Reporting, Recording, Factory, Phasing, Synchronization, Containers, TLM, Components, Sequences, Sequencers, Policies, Register Layer, Macros, Configuration and Resources, Package Scope, and Command Line Processor.
Base Class Library. This provides the basic building blocks that facilitate the design of modular, scalable, and reusable verification components and test environments with the use of uvm_object (which defines an interface of core class-based operations), uvm_component (quasi-static objects such as hierarchical modules and program blocks that exist throughout simulation), and uvm_transaction (which inherits all the methods of uvm_object to include a timing and recording interface).
Predefined Component Classes. These components are the cornerstone of UVM, by encapsulating the behavior of drivers, scoreboards, and other objects in a testbench. The base class library provides a set of predefined component types.
Transaction Level Modeling (TLM). This is a modeling style for building highly abstract models of components and systems based on transactions. UVM provides a set of transaction-level communication interfaces and channels that can be used to connect various components at the transaction level. The use of TLM interfaces ensures that each component remains insulated from changes in other components across the environment. When integrated with UVM’s well-structured framework with the phased, flexible build infrastructure, TLM supports and promotes reusability, enabling the substitution of any component with another, provided they share the same interfaces.
Separating Tests from Testbenches. Tests in terms of stimulus/sequencers are kept separate from the actual test-bench hierarchy and hence there can be reuse of stimulus across different units or across projects.
Modularity and Reusability. The methodology is designed as modular components – e.g.. Driver, Sequencer, and Agents, etc. - which enables reusing components across unit-level to multi-unit-level or chip-level verification as well as across projects.
Simulator Independent. The base class library and the methodology is supported by all simulators and hence there is no dependency on any specific simulator.
Sequence Methodology. This provides robust control over stimulus generation. There are several ways in which sequences can be developed including randomization, layered sequences, and virtual sequences etc. This provides good control and a rich stimulus generation capability.
Reporting Mechanism. This helps in debugging environments with many agents. You can filter and log messages with the help of verbosity. By changing the verbosity, printing messages can be controlled. Severity of messages are classified as fatal, error, warning, info, file name and the line number where file and line are default.

Webinar Video: Don't Be Afraid of UVM (UVM for Hardware Designers)

Hardware Designers are usually very busy doing their work and have little time left for experimentation with new methodologies. Unfortunately for them, official documentation of UVM (Universal Verification Methodology) was written by Verification Engineers for Verification Engineers, concentrating on high-level features, and completely neglecting lower-level details such as connecting UVM testbench to your design. Our webinar starts with a solid review of SystemVerilog interfaces with special attention paid to Virtual Interfaces. Then it proceeds to Sequences and other Data Items, processed by Sequencers and fed to the design under test via Drivers. The role of Monitors and Scoreboards in analysis of results is explained. The presentation concludes with environment configuration and running tests from the top-level module.

Other Webinar Recordings for UVM

Printed version of site: support.aldec.com/en/solutions/functional_verification/uvm_ovm_vmm--emulators-and-debuggers-in-embedded-system

Universal Verification Methodology (UVM)

Primary Use Case

Benefits

Webinar Video: Don't Be Afraid of UVM (UVM for Hardware Designers)

Other Webinar Recordings for UVM

Additional Links