Simulink® Interface in Riviera-PRO


The Simulink Interface built-into Riviera-PRO provides the integration of the Math Works' simulation tools with Aldec’s HDL-based simulation environment for FPGA and ASIC designs. The interface allows designers to co-simulate functional blocks described using mathematical formulas and VHDL entities, Verilog modules, EDIF cells, as well as SystemC modules that are used as black-boxes during the verification process performed within the Simulink environment.

Interface Specification

Software Requirements

Simulink Interface Setup

Step 1 Run Riviera-PRO Setup Program

Follow procedures described below for setting up the Simulink Co-Sim interface:

Printed version of site: