UVM based Verification using Riviera-PRO

Introduction to UVM

Universal Verification Methodology is a standardized methodology for verifying integrated circuit designs written in a Hardware Description Language. It consists of class libraries needed for the development of SystemVerilog based verification environment. It has set of base classes with methods as part of it. Thus, these classes makes it easier to verify the designs used in the industry.

UVM is derived from the Open Verification Methodology (OVM). UVM class libraries brings automation to the SystemVerilog language. It is completely focused upon Object Oriented Programming concepts(OOP). In this app-note we are going to discuss how to use Riviera-PRO for verification purpose using UVM (Universal Verification Methodology).

Why UVM?

UVM is a methodology based on the SystemVerilog language and is not a language on its own. It is a standardized methodology that defines several best practices in verification to enable efficiency in reusability.

Some of the benefits of using UVM are as follows:

Thus, there are many advantages of using UVM for verification purposes. Up next, we will see how UVM based verification takes place using Riviera-PRO.

Next, we will go through UVM’s steps of execution using Riviera-PRO.

Creating Workspace and Design

In Riviera-PRO, individual designs along with their resources can be grouped together as a workspace. The workspace allows adding and working with several designs simultaneously.

Creating Workspace

Creating Design

Design Manager

Creating/Adding Files to Design

Writing UVM

In order to create Verilog/System Verilog/System C design source files or UVM based verification testbenches, double click the Add | New File option. However, here we have provided the UVM based example implementation and we already have the file. So we have chosen Add | Existing File and attached the files that were required for implementation.

UVM Code


Compilation is a process of analysis of a source file. Analyzed design units contained within the file are placed into the working library in a format understandable to the simulator.

Compiling Files

Compiling Designs

Initializing Simulation

Once all needed design units have been compiled successfully, one can initialize simulation. Before initializing simulation, make sure that :

Simulation Initialization

Selecting Testbench as Top level module

Hierarchy Window

Waveform Viewer

Waveform Viewer

UVM Graph Window

UVM Graph Viewer

Printed version of site: support.aldec.com/en/support/resources/documentation/articles/1919