I would like to set a probe in my testbench to monitor a signal inside of the unit under test. How can I make a hierarchical reference to it?
We have similar feature named "Signal Agent". Basically you use Aldec's provided functions to map signals across hierarchical levels:
Example:
signal_agent (<source>, <destination>, <verbose>)
Refer to the Active-HDL documentation (as shown below) for more details on using signal_agent command:
Click on the Help tab.
Select either PDF Documentation or HTML Documentation.
Then, select either option:
For Verilog: click on Using Active-HDL | Compilation | Verilog Compilation | Signal Agent
For VHDL: click on Using Active-HDL | Compilation | VHDL Compilation | Utility Routines | Signal Agent