Port Declaration Orders


Why don't the signals inside blocks on a block diagram (bde) follow the exact same order as representative in the corresponding Verilog/VHDL source code?


Signal order inside the blocks will appear in the same order as in Verilog/VHDL source code for Active-HDL 8.3 and later versions.

Printed version of site: support.aldec.com/en/support/resources/documentation/faq/1135