Add BDE/ASF generated code to Source Revision Control


Is it possible to add BDE/ASF Generated Verilog/VHDL code into a Source Revision Control?


It is possible to add this file to the repository, if you add it to the design. To do so, choose option Add New File and select the option to Make local copy. Active-HDL will then prompt you to add the file to source control.

Note: The new file is read-only by default, but you may change this if so desired.

Printed version of site: