The User:

A fabless semiconductor company requiring:

• Fast verification of 20+MG designs in bit level acceleration and SCE-MI transaction level emulation flow with extensive debugging functions

• Virtual Platform integration in acceleration mode – bit level interface

• Fast back-door access to the memories (different types of DDR and LPDDR)

• Access to debug signals from Testbench and debug API

• Support for designs based on different ARM Cortex processors including big.LITTLE (Cortex A15 and A7) interconnected by AXI bus

How Aldec Delivered:

• Design Verification Manager (DVM) with SCE-MI setup and runtime interface to support transaction based emulation

• DVM with acceleration setup and SystemC testbench support to support bit level verification

• SystemC wrapper allows to connect to Virtual Platform

• SystemC wrapper provides access to debug signals in the testbench

• AXI Master and Slave SCE-MI Macro-Based Xtors

• HES5XLX660EX and HES7XV4000BP boards

• HesDebugApi for fast back-door memory access and signals debugging

• Support for LPDDR2, DDR2, DDR3 and SRAM memory models