The User:
Xelic, an OTN IP Core and Subsystem provider, required:
- SystemVerilog-based simulation capability with:
- UVM support
- Coverage driven constrained random methodology support
- Functional Coverage
- Code Coverage
- Assertions
- GUI interface for debug
- Reasonable simulation performance
- Vendor library support (mainly FPGA)
- Mixed-language support for legacy VHDL/Verilog environments as well as VHDL-only (design and verification)
- A practical licensing price point to support development (mini regressions, GUI, and batch jogs) along with production release to include full multi-seeded batch regressions and coverage