Active-HDL Student Edition

Active-HDL 無料学生版(Student Edition)

Active-HDL Student Edition は、アルデックの混合言語デザイン・エントリ/シミュレーション・ツールを講義期間中、学生が無償で使えるライセンスです。

 

ライセンス

Active-HDL Student Editionのインストールには、製品のライセンスが含まれます。インストール後すぐに使用を開始できます。

 

Active-HDL Student Editionの主な機能

 

Free Active-HDL Student Edition

Active-HDL Student Edition is a mixed language design entry and simulation tool offered at no cost by Aldec for students to use during their course work.

 

Licensing

Active-HDL Student Edition includes a "load and go" license. This means students can begin using it immediately after installing.

 

Key Features of Active-HDL Student Edition

 

Active-HDL Videos

1.1 Basics : Workspace

A Workspace consists of individual designs containing resources such as source files and output files with simulation results. Learn how to create a new Workspace using the New Workspace Wizard, manage an existing Workspace, and manage the different components of the Workspace.

1.2 Basics: Design Flow Manager

In this video, you will learn how to enable the DFM, choose third party vendor tools for synthesis and implementation, and how to access each stage of the synthesis and implementation processes.

1.3 Basics: Library Manager

Learn how to create and manage user libraries, and how to utilize pre-compiled FPGA vendor libraries.

1.4 Basics: Block Diagram Editor

In this video we will take a close look at some essential block diagram editor features that will help you design your BDE file much more easily and smoothly.

1.5 Basics: FSM Editor

This video will demonstrate how to use the State Diagram Wizard and various other features of the editor such as adding states and converting the graphical model into HDL code.

1.6 Basics: HDL Editor

Active-HDL’s HDL Editor is a text editor for editing HDL source code. This video will show how to create a new HDL file with the New Design Wizard and how to utilize the HDE features within that created source file.

1.7 Basics: Compilation and Simulation

Learn how to specify design settings for compilation (setting up debugging windows, selecting maximum optimization, etc.), how to initialize and run simulations, how to view the simulation results, and how to perform compilation and simulation with scripts.



Printed version of site: support.aldec.com/jp/products/fpga_simulation/active_hdl_student