Getting Started with Active-HDL in Efinity

Introduction

This tutorial provides instructions for using Active-HDL in Efinity. Active-HDL is an integrated environment designed for development and verification of VHDL, Verilog, System Verilog, EDIF, and System C based designs. In this tutorial we use a sample Verilog design provided by Efinity to perform design entry and simulation.

Getting Started

It is required to install the latest version of the Efinity software. For Efinity v2025.1, a patch was released — v2025.1.110.2.115. The patch is required to get Active-HDL to work in Efinity. Efinix provides free licenses for the Efinity software; you will need to create an account, log in, and request a license on the Efinity page. You can then download the software and patch from the Efinity Support Center.

It is also necessary to have Active-HDL installed and properly configured to run in the terminal. This means to ensure that the path to Active-HDL is set in your PATH environment variable. You can download the software for free here, but you will need to acquire an Aldec license to use Active-HDL. This tutorial will be using Active-HDL 16.0.

These prerequisites must be done before proceeding further into the tutorial.

Creating Workspace and Design

Open up the File Explorer, go to directory /<path>/Efinity/<Efinity version>/project and create a new folder named helloworld

Figure 1. Creating Project Folder
Open the Efinity GUI.
Once opened, create a new project by going to File > Create Project or click the Create Project button. The Project Editor opens to the Project tab.

Figure 2. Creating project from File

Figure 3. Create Project button
In this tab, type helloworld in the Name box. Then in the Location box, click the button to choose a directory to store project data. Select the /<path>/Efinity/<Efinity version>/project/helloworld directory and click Select Folder.

Figure 4. Naming new project and setting its location
Type a project description in the Description box. For example: “My first Efinity project.”
At the bottom of the Project tab, select Titanium® as the family, and choose Ti60F225 as the device. Keep the default timing model selection.

Figure 5. Selecting FPGA configuration
Click the Design tab.
Type helloworld in the Top Module/Entity box.
Next to the Design box, click the button Import design and constraint files.

Figure 6. Adding files using "Import design and constraint files" option

Now we will be using the example provided by Efinity.
In the Import Directory Files window, navigate to the <path>/Efinity/<Efinity version>/project/tutorial/helloworld directory and choose it. It will automatically add all the design and constraint files found in that directory. (NOTE: You can manually add or remove individual design and constraint files by clicking on the Add/Delete design/constraint file button)

Figure 7. Selecting a directory to add files from

Figure 8. There are options to individually add/remove files
Click OK to close the Project Editor. The Efinity project workspace will be created.

Figure 9. New project workspace
A project helloworld will be created in the Efinity. When you visit the working directory selected in Step 4, an Efinity project file named helloworld.xml is created.

Figure 10. Newly created helloworld.xml file located in design directory

Creating/Adding Files to Design

For creating new files: from the main window dashboard, in the project Project tab, right-click over the desired section and click Create to create a new project file.
For adding existing files: right-click over the desired section and click Add to add existing files.

Figure 11. Add and Create options from right-clicking over Design section

Running Simulation

Open a terminal window.
Type the following commands:
```
> cd \<path>\Efinity\<Efinity version>
> bin\setup.bat
> cd \<path>\Efinity\<Efinity version>\project\helloworld
> efx_run.bat helloworld.xml --flow rtlsim --aldec
```
NOTE: This simulation command assumes the top-level name for the simulation is “sim”. For other designs, add the argument --tb_top <top-level name> at the end to define the testbench name.

The following message will be shown to flag the simulation is successfully completed.

Running: efx_run_sim.py helloworld --sim rtl --family Titanium --device
Ti60F225 --aldec -v ../tutorial/helloworld/helloworld.v,t:default -v
../tutorial/helloworld/helloworld_tb.v,t:default --output_dir outflow --
project_xml C:\Efinity\2025.1\project\helloworld\helloworld.xml

simrtl : PASS

Figure 12. Project simulation run with PASS as final result

The software performs simulation and writes the results to the helloworld.rtl.simlog file in the outflow directory.

Figure 13. Location of helloworld.rtl.simlog

To view the results, select the Result tab from the Efinity software dashboard, click on the triangle side to Simulation to expand the content. Then, double-click helloworld.rtl.simlog to open the log file in the Efinity Code Editor.

Figure 14. Reading simulation results in the Efinity project workspace

The output result is as shown below

KERNEL: --------------Start Helloworld Sim-------------------
KERNEL: Delay size ( 9), Cycle Length ( 512)
KERNEL: LEDs passed initialization
KERNEL: LEDs passed at cycle 0. Actual 00001 matches expected 00001
KERNEL: LEDs passed at cycle 1. Actual 00011 matches expected 00011
KERNEL: LEDs passed at cycle 2. Actual 00111 matches expected 00111
KERNEL: LEDs passed at cycle 3. Actual 01111 matches expected 01111
KERNEL: LEDs passed at cycle 4. Actual 11111 matches expected 11111
KERNEL: LEDs passed at cycle 5. Actual 11110 matches expected 11110
KERNEL: LEDs passed at cycle 6. Actual 11100 matches expected 11100
KERNEL: LEDs passed at cycle 7. Actual 11000 matches expected 11000
KERNEL: LEDs passed at cycle 8. Actual 10000 matches expected 10000
KERNEL: LEDs passed at cycle 9. Actual 00000 matches expected 00000
KERNEL: LEDs passed at cycle 10. Actual 00001 matches expected 00001
KERNEL: LEDs passed at cycle 11. Actual 00011 matches expected 00011
KERNEL: LEDs passed at cycle 12. Actual 00111 matches expected 00111
KERNEL: LEDs passed at cycle 13. Actual 01111 matches expected 01111
KERNEL: LEDs passed at cycle 14. Actual 11111 matches expected 11111
KERNEL: LEDs passed at cycle 15. Actual 11110 matches expected 11110
KERNEL: LEDs passed at cycle 16. Actual 11100 matches expected 11100
KERNEL: LEDs passed at cycle 17. Actual 11000 matches expected 11000
KERNEL: LEDs passed at cycle 18. Actual 10000 matches expected 10000
KERNEL: LEDs passed at cycle 19. Actual 00000 matches expected 00000
KERNEL: LEDs passed at cycle 20. Actual 00001 matches expected 00001
KERNEL: LEDs passed at cycle 21. Actual 00011 matches expected 00011
KERNEL: LEDs passed at cycle 22. Actual 00111 matches expected 00111
KERNEL: LEDs passed at cycle 23. Actual 01111 matches expected 01111
KERNEL: LEDs passed at cycle 24. Actual 11111 matches expected 11111
KERNEL: Reverse direction
KERNEL: LEDs passed at cycle 25. Actual 01111 matches expected 01111
KERNEL: LEDs passed at cycle 26. Actual 00111 matches expected 00111
KERNEL: LEDs passed at cycle 27. Actual 00011 matches expected 00011
KERNEL: LEDs passed at cycle 28. Actual 00001 matches expected 00001
KERNEL: LEDs passed at cycle 29. Actual 00000 matches expected 00000
KERNEL: LEDs passed at cycle 30. Actual 10000 matches expected 10000
KERNEL: LEDs passed at cycle 31. Actual 11000 matches expected 11000
KERNEL: LEDs passed at cycle 32. Actual 11100 matches expected 11100
KERNEL: LEDs passed at cycle 33. Actual 11110 matches expected 11110
KERNEL: LEDs passed at cycle 34. Actual 11111 matches expected 11111
KERNEL: LEDs passed at cycle 35. Actual 01111 matches expected 01111
KERNEL: LEDs passed at cycle 36. Actual 00111 matches expected 00111
KERNEL: LEDs passed at cycle 37. Actual 00011 matches expected 00011
KERNEL: LEDs passed at cycle 38. Actual 00001 matches expected 00001
KERNEL: LEDs passed at cycle 39. Actual 00000 matches expected 00000
KERNEL: LEDs passed at cycle 40. Actual 10000 matches expected 10000
KERNEL: LEDs passed at cycle 41. Actual 11000 matches expected 11000
KERNEL: LEDs passed at cycle 42. Actual 11100 matches expected 11100
KERNEL: LEDs passed at cycle 43. Actual 11110 matches expected 11110
KERNEL: LEDs passed at cycle 44. Actual 11111 matches expected 11111
KERNEL: LEDs passed at cycle 45. Actual 01111 matches expected 01111
KERNEL: LEDs passed at cycle 46. Actual 00111 matches expected 00111
KERNEL: LEDs passed at cycle 47. Actual 00011 matches expected 00011
KERNEL: LEDs passed at cycle 48. Actual 00001 matches expected 00001
KERNEL: LEDs passed at cycle 49. Actual 00000 matches expected 00000
KERNEL: --------------Helloworld Passed-------------------

The designed logic is successfully validated, and you can continue to build the peripheral portion using Efinity Interface Designer. For more information, please refer to the Efinity User Guide.

Viewing Simulation Waveform

Upon initializing a simulation through Active-HDL’s simulator, an .asdb file automatically gets generated. This file can be opened to view the logged simulation signals through Active-HDL’s Waveform Viewer. To log signals into the .asdb file, Active-HDL allows you to use the task $asdbDump for Verilog testbenches or the procedure asdbdump for VHDL testbenches. For VHDL, you will need to include the following library and use clauses in your testbench:

library aldec;
use aldec.aldec_tools.all;

For this tutorial we will be using the Verilog task $asdbDump.

In helloworld_tb.v, at the beginning of the body of the initial begin statement on line 44 underneath the $dumpvars line, add in the following command:

$asdbDump (0, 0, sim);

This task will record all the signals from the top-level sim.

Figure 15. Adding $asdbDump into helloworld_tb.tv through Efinity's Code Editor
Save the changes. Then back in the terminal, run the same efx_run.bat command as seen previously in the Running Simulation section. The test should pass again.
Open Active-HDL through the current terminal using the command avhdl.

Figure 16. Active-HDL 16.0 opens upon using avhdl command in terminal
A wave.asdb file should be in the helloworld folder. Open it by typing open -asdb wave.asdb into the Console in Active-HDL.

Figure 17. Showing wave.asdb location and the open command in the Active-HDL Console
The recorded signals and their values from the simulation run should now be displayed in the Waveform Viewer.

Figure 18. The simulation results in the Active-HDL Waveform Viewer
You can now utilize the many options the Waveform Viewer has such as:
- Adding comments to your waveform
- Grouping your signals however you like
- Bookmarking parts of your waveform
- Changing visual properties of signals on the waveform such as color
- Browsing through signals history based on event, rising/falling edges, etc.

For more details on the Waveform Viewer, please check out our video on this tool here. In the Active-HDL GUI, you can also go to Help > PDF/HTML Documentation > Product Help and search for “Waveform Viewer” for even more details.

(NOTE: Some options within the Waveform Viewer may be unavailable in post-simulation viewing)

HELP

Go to Aldec Support to access the online database and other technical documents about Active-HDL.

Register or use your Aldec support account at https://www.aldec.com/support to open a support case or download the software.