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Name Products Type Action
ASIC プロトタイピング - Xilinxとの共著   
本論文では、最新のVirtex-7デバイスおよびVirtex-7 2000Tを2つ搭載したAldec HES-7プロトタイピング・ボードに注目し、FPGAベースのプロトタイピングを使用したASIC検証の可能性について説明しています。また、最も一般的なパーティショニングの問題と解決策について記載されています。
HES-DVM, HES™ Boards ホワイトペーパー
Accelerate SoC Simulation Time of Newer Generation FPGAs   
Comprehensive verification that can be provided by HDL simulators is good, but not ideal. What is necessary is a faster, safer, and more thorough verification environment that combines the robustness of an HDL simulator with the speed of FPGA prototyping boards. The goal is to put together the power of these two verification methodologies into one platform.
HES-DVM ホワイトペーパー
Debugging SCE-MI Co-Emulation in Riviera-PRO   
Abstract: Debugging a design during emulation with a high level of visibility can be a challenge. This paper presents Aldec’s solution to this problem; a debugging environment for SCE-MI co-emulation that provides 100% signal visibility of the design running in an FPGA-based emulator. Debug probes captured intelligently from emulator retain original signals names and hierarchy paths to provide true RTL view of design in emulation.
Riviera-PRO, HES-DVM ホワイトペーパー
Designing UVM Testbench for Simulation and Emulation of Network-on-Chip Design   
Universal Verification Methodology (UVM) is one of the most popular approaches in using transactional testbench environment. The growth of SoC designs forces design and verification teams to use emulation as a way to speed-up verification process. Standard CoEmulation Modeling Interface (SCE-MI) provides ways to connect emulated design with transactional testbench. This paper describes how to use SCE-MI to create UVM test environment that is ready for both simulation and emulation.
HES-DVM ホワイトペーパー
HDL Simulation Acceleration Solution for Microchip FPGA Designs   
Mission-critical FPGA designs for space and radar applications continue to increase in complexity, such that they require a comprehensive and robust verification environment. There are hardware-in-the-loop solutions in the market that utilize FPGA boards, but when it comes to establishing functional coverage and debugging the custom logic, users would typically need to go back to HDL simulation. As a result, HDL simulations are becoming excessive and they have become the primary bottleneck when it comes to verification. In this paper we will describe a solution that can accelerate HDL simulation for the system FPGA design that includes the custom logic and reused IP Cores where the testbench executes in the simulator and the synthesizable parts of the design is implemented in a Microchip FPGA board.
Riviera-PRO, HES-DVM, HES™ Boards ホワイトペーパー
Meeting Growing Verification Demands   
Abstract: The first decade of the 21st century brought tremendous growth of the size of typical digital design, triggering growing demands for faster, safer and more thorough verification. In response to those demands, many new flavors of verification were invented and implemented in the tools, making engineers face difficult choices. This paper gives detailed overview of currently available verification methodologies suitable for large designs and shows how Aldec tools can help in their implementation.
Riviera-PRO, HES-DVM ホワイトペーパー
SCE-MI に決まっているじゃないですか。でも、どれなのだろう?   
SCE-MI 2の3つのユースモデル(マクロベース、ファンクションベース、パイプベース)について。その違い、ユースケース、推奨について
HES-DVM ホワイトペーパー
Simulation Acceleration with HES XCELL   
Abstract: Comprehensive verification that can be provided by HDL simulators is good, but not ideal. What is necessary is a faster, safer and more thorough verification environment that combines the robustness of an HDL simulator with the speed of FPGA prototyping boards. The goal is to put together the power of these two verification methodologies into one platform.
HES-DVM ホワイトペーパー
SoC verification made easy with Aldec HES-DVM   
As designs grow larger, the time spent verifying a project is growing longer as well. As a solution, some companies are trying to ‘shift-left’ their schedules. Verification via software simulators is not fast enough for large System-on-Chip (SoC) design projects, therefore one option is to use an FPGA emulator to speed up the design process. But what happens when a bug occurs? This document describes Aldec® HES-DVM™ features that can help speed up debug and verification of the SoC, in order to achieve faster time-to-market.
HES-DVM ホワイトペーパー
Using FPGA Based Simulation Acceleration in Typical ASIC Design Flow   
Abstract: Typical ASIC front-end and back-end implementation process involves HDL simulation as a method of verifying design netlist functionality at each stage of the flow. Although HDL simulation is considered accurate it suffers from very low execution speed.Aldec provides the DVM software that allows reusing your existing FPGA prototyping board as a platform for hardware acceleration of HDL simulation.
HES-DVM, HES™ Boards ホワイトペーパー
Using FPGA Prototyping Board as an SoC Verification and Integration Platform   
Abstract: Size of new designs has grown so much that it easily allows creation of the entire system containing microprocessor unit and peripherals on one chip. Verification of such designs can no longer rely on software only, since simulation of MPU does not allow fast enough testing of application software and formal tools handle system hardware only. The use of FPGA-based prototyping boards creates fast and economical solution to this problem. This paper presents one practical implementation of Prototyping Board Verification and Integration Platform.
HES-DVM, HES™ Boards ホワイトペーパー
Verification of Ethernet Designs with SCE-MI based Aldec Emulator   
Abstract: This white paper presents how to use modern verification techniques for advanced ASIC and SoC designs. Network based application has been selected for this study as a real life design project. Verification process will be performed using Aldec hardware emulation system called HES with transaction based SCE-MI interface used for testing activities. The key objective is to perform the verification of the Ethernet Network Switch with real data delivered directly from Ethernet network in very limited time assigned for verification setup process.
HES-DVM ホワイトペーパー
Virtual Modeling with Aldec and Imperas   
Abstract: Virtual platforms play a significant role in system level development, but they require the speed that emulation systems provide for hardware/software co-verification. This white paper describes a high performance virtual modeling solution achieved by integrating Aldec’s Transaction Level Emulation System with Imperas’ OVP™ (Open Virtual Platforms) and OVPsim™ (OVP simulator). Hardware and Software design teams are now able to simulate and debug virtual models of processors, memories and peripherals while the rest of the system resides in the emulator board running at MHz clock speeds.
HES-DVM ホワイトペーパー
マルチFPGAプロトタイピングにおける パーティショニングの課題   
ASIC/SoCデザインのマルチFPGAによるプロトタイピングは、エミュレーション技術の中で最も高いクロックレートを実現します。しかし、プロトタイピングのためのデザインセットアップは非常に複雑で困難です。このホワイト ペーパーでは、デザインを複数の FPGA にパーティショニングする際の一般的な課題を明らかにし、プロトタイプの品質を向上させ、デザインのセットアップにかかる時間を短縮するソリューションを提供します。
HES-DVM, HES™ Boards, HES-DVM Proto Cloud Edition ホワイトペーパー
14 results
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