STATIC DESIGN VERIFICATION
ALINT-PRO™
Static RTL verification focused on finding structural, coding and clock/reset-domain issues before simulation and synthesis.
CAPABILITIES
Designed for productive verification.
RTL linting
Automated checks for coding defects, portability and synthesis-related issues.
CDC / RDC
Analyze clock and reset domain crossings and potential metastability risks.
Design rule checking
Apply configurable rule libraries to VHDL, Verilog and SystemVerilog RTL.
Safety-critical workflows
Rule libraries and qualification-oriented workflows for high-assurance projects.