SoC, ASIC & ASSP Prototyping in FPGA
Whether the design targets an ASIC, ASSP or FPGA, design prototyping is an essential verification methodology in every IC project. Prototyping can be implemented in various hardware configurations and technology depending on the design complexity, but in all cases the use of FPGA-based platforms have become the de-facto due to the versatility and maturity of FPGAs. The wealth of the FPGA marketplace facilitates finding the appropriate FPGA parts that satisfy the required number of DSP, RAM and logic resources for most applications. Besides the basic logic elements known as primitives, today's FPGAs contain complex blocks like microprocessor subsystems or peripheral PHY blocks enabling implementation of Systems-on-Chip (SoC) with high speed communication interfaces and various standards like PCI Express, USB, SATA, QSFP+ and the like.
Building the prototyping platform from the ground up with such complex FPGA devices would be both time consuming and risky. Aldec’s HES™ Prototyping Platform and related solutions mitigate these risks and facilitate rapid implementation of reliable prototype.
Designing state-of-the-art FPGA prototyping boards involves several months of development, production and testing, and can only be successfully completed by a team of experienced hardware designers. Choosing the appropriate commercial-off-the-shelf (COTS) hardware platform for design prototyping is key to success, and can help you save plenty of time and resources in the project schedule.
Aldec HES Prototyping Platform is a complete solution incorporating the most powerful FPGA devices that provides a scalable logic resources and is complemented by the rich choice of peripheral daughter cards compliant with the FMC interconnect standard.
Closing the loop with various verification tools is possible thanks to the HES Proto-AXI Interconnect. It utilizes the PCI Express high speed link to connect HES boards to a workstation host or high speed serial IO GTX lanes to connect to an embedded host, which is a Zynq device with ARM Cortex-A processor. The design can be connected to the well known AMBA AXI4 interface. Easy to use C/C++ API and Python wrapper are provided on Linux and Windows operating systems to enable rapid development of test environment.
Prototyping with FPGAs promises to deliver the fastest run of all verification tools, but unfortunately brings challenges when it comes to multi-FPGA design setup that include complex partitioning, arranging interconnections and managing multiple clock domains across multiple devices. EDA tool support in this field is highly desirable in order to avoid time consuming/error prone hand-crafting and in some cases, design hacks that would be necessary only to enable FPGA prototyping. Addressing these challenges, Aldec provides HES-DVM Proto tool that contains new partitioning utilities and can convert ASIC clocks to FPGA-proof structures. Awareness of clock domains and prototyping board connectivity resources brought by HES-DVM Proto facilitates in making wise decisions and allows achieving high clock ratios of FPGA prototypes.
The HES provides support for ARM® dual-core Cortex™-A9 MPCore™ application development, leveraging Xilinx Zynq™ All Programmable 7000 and MPSoC Series. Designers can now leverage the serial processing capabilities of the ARM Cortex-A9 processor for projects that require general purpose computations with the parallel processing capabilities of the largest FPGAs to implement applications across a diverse range of markets or utilize ARM processor to implement on-board embedded software driven testbench.
Our RTAX/RTSX prototyping solution provides a reconfigurable platform for Microchip RTAX-S/SL, RTAX-DSP, and RTSX-SU space-flight design systems. Unlike traditional OTP (One Time Programmable) antifuse space-qualified FPGAs, the Aldec prototype adapter utilizes Microchip™ ProASIC3E FPGAs, allowing designers to prototype their design with greater routing flexibility, more switches, lower power consumption, non-volatile re-programmability, and Netlist optimization.
Scalable HES™ Prototyping PlatformHES Proto-AXI InterconnectMulti-FPGA Design PartitioningARM Cortex SupportRTAX/RTSX Prototyping