Name Products Type Action
IRセンサーは、COVID-19パンデミック時の主要な安全対策の1つである非接触型の人体温度測定に非常に役立ちます。 熱センサーデータを標準のカメラ画像およびAIベースのコンピュータビジョンアルゴリズムと組み合わせることで、全体的な温度スクリーニングプロセスを自動化し、大幅に改善することができます。
TySOM Boards, TySOM™ EDK チュートリアル
4K Motion Detection Using Optical Flow on TySOM Kit   
Image data resolution is constantly growing in different applications and 4K UltraHD resolution is a standard nowedays. We will demonstrate that Aldec TySOM board which based on Xilinx Zynq FPGA can be successfully used in application and FPGA chip can accelerate functions and algorithms to achieve high performance.
TySOM™ EDK デモンストレーションビデオ
4K Video Processing Using TySOM Board   
In this video, we showcase Aldec's 4k video transferring reference design using Xilinx Zynq based SoC FPGA device on TySOM-3-ZU7EV board. In this demo, two TySOM-3-ZU7EV board are connected using high data bandwidth interface (QSFP+).
TySOM™ EDK デモンストレーションビデオ
Addressing the Challenges of SoC Verification in practice using Co-Simulation   
Heterogeneous System on Chip (SoC) devices like the Xilinx Zynq 7000 and Zynq UltraScale+ MPSoC combine a high-performance processing systems (PS) with state of the art programmable logic (PL). This combination allows system to be architected to provide an optimal solution. Verifying this interaction between the PS and PL presents a challenge to the design team. While each can be verified in isolation using QEMU for the PS and Riviera-PRO for the PL. The integration between the PS and PL all too often takes place late in the design cycle when the impact of addressing issues raised is larger in both time and cost. There is however, another way which is Co-Simulation, which can be performed early in the development cycle. This webinar will explore the challenges which are faced by SoC users, introduce the concept of Co-Simulation and its constituent parts along with demonstrating advanced debugging techniques. We will examine the required environment and pre-requisites needed to perform Co-Simulation. Detailed examples will then be presented to demonstrate basic and advanced debugging concepts. Based upon a Zynq implementing a Pulse Width Modulation IP core operating under SW control. We will look at examples which introduce basic Co-Simulation flow like waveform inspection along with advanced debugging aspects such as software and Hardware breakpoints and single stepping. These techniques will enable us to identify and debug issues which reside in both the software and hardware design. Co-Simulation enables you to develop your application faster and reduce the bring up time once the application hardware arrives for integration. This webinar will demonstrate these benefits and more which are gained when Co-Simulation is used, while demonstrating the ease with which the environment can be established and simulation performed. Play webinar   
Riviera-PRO, TySOM™ EDK ウェブセミナーの録画
Advanced RTL Debugging for Zynq SoC Designs   
Presenter: Radek Nawrot, Aldec Software Product Manager

Abstract: Designers of complex embedded applications based on Xilinx® Zynq™ device require a high-performance RTL simulation and debugging platform. In this webinar, you will learn several advanced RTL debugging methodologies and techniques that you can employ for your block-level and system level simulation. You will learn how to use Dataflow, Code Coverage, Xtrace and Waveform Contributors for analyzing the errors in your AXI-based Zynq designs.

We welcome you to refer to the following Application Notes prior to the webinar:
Xilinx AXI-Based IP Overview
Simulating AXI BFM Examples Available in Xilinx CORE Generator
Simulating AXI-based Designs in Riviera-PRO
Performing Functional Simulation of Xilinx Zynq BFM in Riviera-PRO

  • Embedded development flow between Xilinx Vivado™, SDK™, Riviera-PRO™ and TySOM™
  • Quick introduction to AXI
  • Running Riviera-PRO from Vivado
  • Code Coverage in simulation process
  • Advance dataflow- design overview
  • Bug injection – Xtrace in action
  • Waveform with Contributors – seek bug in code
 Play webinar   
Riviera-PRO, TySOM™ EDK ウェブセミナーの録画
Basic UART Interface Tutorial TySOM-1-7Z030   
In this tutorial, you will learn how to use UART to interface the TySOM-1-7Z030 board with other systems. The UART interface enables us to view serial output from the board which can be useful for monitoring. This project has both a hardware and software part.
TySOM-1, TySOM™ EDK チュートリアル
Connecting Leopard camera to TySOM-3-Zu7EV board using FMC connector   
This demo design uses TySOM-3-ZU7EV board to capture the LI_IMX274MIPI camera 4K video through the FMC HPC connector on the board and show it on a screen. LI-IMX274MIPI-FMC is a high-resolution digital camera board. It incorporates a Sony 1/2.5" CMOS digital image sensor with an active imaging pixel array of 3864H x2196V.
TySOM™ EDK チュートリアル
Designing FPGA-based ADAS Application - Driver Drowsiness Detection   
Advanced Driver Assistance Systems (ADAS) provide a significant contribution to increasing automotive safety. ADAS systems provide the driver with increased situational awareness, helping to reduce collision and accidents. To provide the driver with increased situation awareness ADAS systems can be categorized as providing external or internal awareness. External ADAS systems monitor such aspects as blind spots and lane detection, while internal systems monitor the occupants and particularly the driver themselves such as Driver Drowsiness Detection. Both internal and external ADAS systems rely heavily upon embedded vision systems, implementing these embedded vision systems depending upon the task at hand can be computationally intensive. This computational complexity can reduce the performance of the system introducing latency and reducing the validity of the information provided to the driver. The use of hardware programmable logic enables the implementation of a low latency high performance system. However, industry standard development techniques such as the use of OpenCV cannot be used due to high development cost and timescales. This webinar will demonstrate how an ADAS driver drowsiness detection application can be implemented using a Zynq heterogeneous SoC which combines programmable logic with high performance ARM cores. This example will demonstrate how a System Optimizing Compiler can be used in conjunction with the Zynq to create the ADAS application using high level languages and industry standard frameworks. The use of the System Optimizing Compiler enables seamless acceleration of C functions into the programmable logic, enabling a significant performance increase.  Play webinar   
TySOM™ EDK ウェブセミナーの録画
DIPスイッチを使用してLEDを点滅させるための ハードウェアとソフトウェアプロジェクトの作成 TySOM -1-7Z030   
このチュートリアルでは、Xilinx Vivado Design Suiteでハードウェアプロジェクトを作成し、Xilinx SDKでTySOM-1-7Z030ボード用のソフトウェアプロジェクトを作成する方法を学習します。最初にハードウェアから作成し、オンボードのスイッチを使用してオンボードLEDを点滅させるソフトウェアアプリケーションを作成します。このチュートリアルの最後では、JTAG programmerを使用してTySOM-1-7Z030ボードでプロジェクトをプログラミングする方法についても学習します。microSDカードを使用してFPGAをプログラムするには、「MicroSDカードを使用してTySOM-1-7Z030ボードをプログラミングする」チュートリアルに従います。
TySOM-1, TySOM™ EDK チュートリアル
DNN Based Object Classification on TySOM Kit   
Object detection by a Neural Network is a hot topic nowadays in many fields such as automotive or industrial. Accurate and fast detection and classification is required. These requirements can be fulfilled with system based on FPGA accellerated SoC chips such as Xilinx Zynq. In this presentation we will demonstrate how to utilze Aldec TySOM board for object detection and recognition application.
TySOM™ EDK デモンストレーションビデオ
Enabling GPIO Interrupts Tutorial TySOM-1-7Z030   
An interrupt is a signal that temporarily halts the processor’s current activities and demands immediate attention. The processor saves its current state and executes an interrupt service routine to address the reason for the interrupt. Real-time designs require interrupts because many systems will have a number of inputs (e.g. keyboards, mouse, pushbuttons etc.) that will require processing. Inputs from these devices are generally asynchronous to the execution of running processes or tasks, so you cannot always predict when the event will occur. Using interrupts enables the processor to continue processing until an event occurs, at which time the processor can address the event. This interrupt-driven approach also speeds up the response time. This basic GPIO interrupt design is intended to enable GPIO interrupts to users on the TySOM-1-7Z030 board. The standard flow includes several stages to create a hardware platform for the Zynq-7000 based board.
TySOM™ EDK チュートリアル
FMC ADAS CARD Technical Specification   
FMC ADAS CARD Overview, Block Diagram, Interfaces, etc.
FMC-ADAS, TySOM™ EDK Technical Specification
FMC-ADAS Technical Specification    FMC-ADAS, TySOM™ EDK Technical Specification
FMC-INDUSTRIAL Technical Specification   
FMC-INDUSTRIAL Technical Specification
FMC-INDUSTRIAL, TySOM™ EDK Technical Specification
FMC-INTF Technical Specification    FMC-INTF, TySOM™ EDK Technical Specification
FMC-IoT Technical Specification    FMC-IOT, TySOM™ EDK Technical Specification
FMC-NET Technical Specification    FMC-NET, TySOM™ EDK Technical Specification
FMC-QSFP Technical Specification    FMC-QSFP, TySOM™ EDK Technical Specification
FMC-Vision Technical Specification    FMC-VISION, TySOM™ EDK Technical Specification
FPGA Accelerator for Genome Aligner - ReneGENE   
Aldec industry partner, ReneLife introduces its proprietary core technology, ReneGENE, for fast and accurate alignment of short reads obtained from the Next Generation Sequencing (NGS) pipeline. The technology, devoid of heuristics can precisely align the DNA reads against a reference genome at a single nucleotide resolution. As genomics permeates the entire landscape of biology, including biomedicine and therapeutics, ReneGENE creates a genomic highway that significantly contributes to reduce the time from sample to information without compromising on accuracy, critical for lifesaving medicare applications, biotechnology product development and forensics.

In this webinar, we present AccuRA, a high-performance reconfigurable FPGA accelerator engine for ReneGENE, offered on Aldec HES-HPC™ for accurate, and ultra-fast big data mapping and alignment of DNA short-reads from the NGS platforms. AccuRA demonstrates a speedup of over ~ 1500+ x compared to standard heuristic aligners in the market like BFAST which was run on a 8-core 3.5 GHz AMD FX™ processor with a system memory of 16 GB. AccuRA employs a scalable and massively parallel computing and data pipeline, which achieves short read mapping in minimum deterministic time. It offers full alignment coverage of the genome (million to billion bases long), including repeat regions and multi-read alignments. AccuRA offers a need-based affordable solution, deployable both in the cloud and local platforms. AccuRA scales well on the Aldec platform, at multiple levels of design granularity.

  • Introducing the world of genomic big data computing
  • The need for accuracy and precision
  • Introducing ReneGENE/AccuRA
  • Product Demo
  • Impact of ReneGENE-The Genomic Highway
Presenter: Santhi Natarajan, Ph. D (IISc) Play webinar   
Riviera-PRO, HES-DVM, TySOM™ EDK ウェブセミナーの録画
73 results (page 1/4)
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