Company Newsroom Industry’s First use of TLM for the At-Speed Verification of a PCIe-Based Avionics Design Requiring DO-254 Compliance Release Feb 14, 2022 Productivity Through Methodology: Aldec Adds UVM Generator to Riviera-PRO™ Plus Updates Its OSVVM and UVVM Libraries Release Nov 16, 2021 New HES Board is Ideal for Prototyping and Emulating Medium to Large ASIC & SoC Designs Release Aug 16, 2021 New TySOM-M Series Targets Low Power, High Security Applications Release Jul 7, 2021 Aldec Launches HES-DVM Proto ‘Cloud Edition’ - Giving Engineers Easier Access to FPGA-based ASIC & SoC Prototyping Release Jun 2, 2021 Airborne System Design Assurance: Aldec Adds 60+ New HDL Rules to ALINT-PRO’s DO-254 Plug-In Release Mar 4, 2021 Powerful FPGA Design Creation and Simulation IDE Adds VHDL-2019 Support & OSVVM Enhancements Release Jan 20, 2021 RECENT NEWS ALINT-PRO™ Adds New Mixed-Language Design Rules for More Predictable Cross-Language IntegrationRelease JAN 14, 2026What’s involved in simulation of a complex SoC FPGA like Versal ACAP?In the News FEB 08, 2024Aldec @ DAC 2023: Presenting Design Verification Tools and Solutions for FPGAs and SoCsRelease JUN 26, 2023Riviera-PRO Supports System Simulation of AMD® Versal™ ACAP DesignsRelease JUN 14, 2023The avionics industry’s growing need for TLMIn the News MAY 18, 2023Aldec and Thales to Co-Present at Certification Together International Conference 2023Release MAY 01, 2023 view all news RECENT YOUTUBE VIDEOS 2.13 - Active-HDL™ (v17) Active-HDL Debugging: Performing Step Simulation 3.7 - Active-HDL™(v17) 3rd Party Flows: Simulating Efinix IP and Designs with Active-HDL Riviera-PRO™- 3.6 Interfacing: Using the New AI Assistant Rivera-PRO™ (v.2025) - 1.14 Basics: Converting ModelSim® Macros and Projects view all videos RECENT BLOG ARTICLES Bridging Simulation and Hardware Hardware-in-the-Loop in Action Advanced Static Linting for FPGA Performance Optimization How to Boost Design Speed and Efficiency Scalable Cloud-based CI/CD HDL Verification Environment Enhance Your Verification Workflow with Azure, VUnit, and Riviera-PRO Navigating VUnit: A Practical Guide to Modifying Testing Approaches Speeding Up Simulation with VUnit for Parallel Testing view all articles UPCOMING EVENTS Enhancing CDC Verification in Vivado with ALINT-PROWebinar OCT 28, 2026Practical LLM Techniques for FPGA Functional Verification (US)Webinar OCT 29, 2026Practical LLM Techniques for FPGA Functional Verification (EU)Webinar OCT 29, 2026Modeling AMD Zynq MPSoC PS8 Interfaces with OSVVM (EU)Webinar NOV 12, 2026 view all events
