UVM Simulator Are you tired of waiting for traditional HDL simulations to catch up with the pace of your ever-expanding ASIC designs? The need for speed in the design cycle is crucial, and limitations in simulation times can be a major bottleneck. Schedule a Consultation Introducing Riviera-PRO - High-Performance UVM Simulator with UVM Testbench Generator Riviera-PRO unleashes the power of UVM simulationfor FPGA and SoC FPGA designs. Assemble powerful test environments with functional coverage and constrained random stimulus generation. Simplify testbench development with UVM testbench generator, RAL generator and UVM Graph. Increase IP and testbench reusability from block-level to system-level across multiple projects. Advanced Debugging Capabilities Navigate through your designs effortlessly with our suite of advanced debugging tools. From the UVM Toolbox and UVM graph to the Class Viewer, our simulator empowers you to visually map and debug designs based on OVM/UVM class libraries. Built-in debugging features include code tracing, waveform analysis, dataflow exploration, FSM window, coverage evaluation, assertion debugging, and memory visualization - all to streamline your debugging process. Benefits of adopting Universal Verification Methodology (UVM) Reduce the cost of reusing IPs with new projects Reuse verification components from block-level to system-level Lower verification costs Improve design quality Why Choose Riviera-PRO? Extensive simulation optimization algorithms to achieve the highest performance in VHDL, Verilog/SystemVerilog, SystemC, and mixed-language simulations. Industry-leading capacity and simulation performance enabling high regression throughput for developing the most complex systems. Support for advanced verification methodologies including UVM, OSVVM, UVVM, cocotb and VUnit. Integrated multi-language debug environment enables automating time-consuming design analysis tasks and fixing bugs quickly. UVM Toolbox, UVM graph, Class Viewer, Transaction streams and data to allow visual mapping and debugging of designs based on OVM/UVM class libraries. Built-in debugging tools provide code tracing, waveform, dataflow, FSM window, coverage, assertion, and memory visualization capabilities. Comprehensive Assertion-Based Verification (SVA and PSL) for increased design observability and decreased debug time. Don't let slow simulations hinder your progress. Embrace the future of UVM simulation acceleration with Riviera-PRO and witness unparalleled speed and efficiency in your verification process. Try Riviera-PRO today and elevate your ASIC design verification to new heights! Try Free Trial Get Advice Product Videos Advanced: UVM Toolbox Take a look on how to make use of the UVM Toolbox available in Riviera-PRO for debugging designs and making the most of your verification environment. Use the UVM Viewer, UVM Hierarchy, and UVM Configuration windows to represent UVM architecture and their TLM connections to improve the perspective of the architecture and dataflow. Watch Advanced: UVM Register Generator The UVM Register Generator is used to create Register Model files to incorporate into a UVM environment to use the Register Abstraction Layer of UVM. Automatically generating models for the RAL is particularly time saving, considering modern designs can consist of thousands of registers, and coding those by hand would be a long and tedious task, while still being a crucial aspect of the verification of the design. Watch Debugging: UVM Transactions Debugging Riviera-PRO provides the Transaction Level Modeling (TLM) interfaces for use with VHDL, Verilog/SystemVerilog, and SystemC industry standard languages. The TLM interfaces have been also implemented in the SystemVerilog UVM/OVM and SystemC Verification (SCV) libraries delivered with Riviera-PRO. Watch Debugging: Xtrace and Advance Dataflow Visualizing the hierarchy and the connectivity of an active design and analyzing the dataflow among the instances, concurrent statements, nets and registers. Monitoring the design for undesired and unknown values using Xtrace. Combining Xtrace with Advanced dataflow for quick exploration of the drivers of unknown values. Watch Accelerating UVM Verification with Emulation In this video, Application Engineer Henry Chan, explains how emulation can help accelerate UVM-based testbenches and explores the benefits of emulation/acceleration over traditional simulation tools. A cursory overview of the Accellera SCE-MI standard as well as some necessary testbench modifications for emulation/acceleration are presented. Watch Jenkins with Riviera-PRO Jenkins is an open source automation server allowing for continuous integration of HDL design in a collaborative environment. In collaboration with Riviera-PRO's batch mode, Jenkins can periodically poll shared repositories belonging to a design team and execute build orders on the detection of source code modifications. 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