Aldec in the Classroom

Aldec’s University  Program is committed to providing future engineers with world-class tools for their digital system designs and verification methodologies.  These tools are offered at a lower cost to educational facilities who meet the university program requirements. In addition, students  are able to download the free Active-HDL™ Student Edition which allows them to use the design entry and simulation tool throughout their coursework.

Students and faculty are also provided with access to online resources such as whitepapers, webinars, and demonstrations. Aldec takes pride in its commitment to tomorrow’s engineers, and often sends engineers to deliver onsite presentations to students and faculty on the latest research in the field of system verification. Aldec recently presented as part of the VLSI Design & Test Seminar Series by Auburn University. This series seeks to provide an open forum for various faculty, graduate and undergraduate students with research and development efforts in the area of design and test of VLSI systems, including application specific and programmable circuits in digital, analog, and mixed-signal microsystems.

Aldec visited Auburn University this past month for a seminar on a paper to be presented during this year’s Military and Aerospace Programmable Logic Devices (MAPLD) conference. The paper titled, “Hybrid Platform for High Capacity FPGA Validation and Verification”, showcases the Hardware Emulation Solution (HES) ecosystem, a complete validation and verification platform for large capacity SoC and ASIC designs.  During the visit, Aldec Research Engineer and Auburn graduate, Bill Jason Tomas, presented different modes of validation and verification including: simulation acceleration, prototyping, and transaction level emulation. Tomas also presented many debugging capabilities of Aldec’s hardware emulation application, HES-DVM™, to quickly debug and diagnose system-level faults occurring in a design.

Tomas also visited digital design classrooms to showcase Aldec’s FPGA design and verification tools, Active-HDL™ and Riviera-PRO™.  In these demonstrations, Tomas utilized examples from classroom activities and displayed how students can utilize Aldec tools to develop, debug, and verify their own digital systems.

“It was a great experience giving back to my alma mater, and providing them with tools which will help them with their studies”, stated Tomas during an interview with faculty.

For more information on attaining Aldec tools for your university or having an Aldec engineer provide in-class demonstrations, contact Aldec or visit www.aldec.com/en/products/university_programs.