Effective Communication is Key in Relationships… and ESL Design!

Aldec & Agilent EEsof improve digital/ESL relationship with COMRATE™ engine

Mariusz Grabowski, FPGA Design and Verification Engineer
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COMRATE™, the co-simulation solution developed by Aldec and Agilent is a lot like “couples-therapy” that can help get your digital blocks talking to the rest of your model-based design.

To illustrate, let’s take a look at a very basic model-level design and think about it from design-under-test perspective (i.e., what are the challenges associated with verifying this DUT):


This is a simple  modulator system that utilizes the fixed-point and HDL models.

  • The schematics instantiates carrier and input sources, the floating-point to fixed-point converters, and two subsystems running at different rates.
  • The arrow-shaped block connecting the two subsystems performs interpolation with a factor of two, i.e. doubles the clock rate.
  • The first subsystem (marked blue) contains a multiplier which runs at a 1MHz clock rate; the second subsystem (marked green) runs twice as fast, and is the simplest example of a processing path – a single gain block.
  • It’s a multirate design, since it includes blocks driven by multiple clocks derived from the same source.

So what are the challenges in verifying a multirate design like this one?


Alright, communication was the obvious one… a simulation/verification environment is required to help stitch together different levels of abstraction, enabling the model-level and digital/RTL blocks to talk to each other. An environment like the one presented in the following diagram:



But there is another, less obvious pitfall due to the nature of event-driven (HDL) and dataflow (system-level) simulation schemes. Consider this:


  • The HDLs are designed to model the parallelism of hardware using computers, which execute the code sequentially. (Implying that all design nodes have the same simulation time, and the simulation time cannot decrease in subsequent simulation steps).
  • As opposite to the HDL simulation, the chronology of samples in the subsequent system-level simulation steps is preserved only for a block, but not for the entire system.

Therefore, the following “back in time” scenario is possible for a given point of simulation in a multirate system:


  • A slower block ‘B’ stays in tB9 (0) time.
  • A faster block ‘A’ reaches tA9 (7) which is greater than tB9 (tAcurr > tBcurr).
  • The ‘B’ is executed at tB10 (4) which is less than tA9 (tBnext < tAcurr)


These fundamentally different execution schemes impose constraints on the verification environment which therefore must combine a multirate system-level simulator (utilizing a non-chronological execution scheme) with an HDL simulator (which cannot move backwards by definition). On top of this, efficient debugging tools are required to visualize the simulation results…

We have just scratched the surface on this topic. In other words, this was just the trailer! To see the entire “movie” I invite you to download our newest white paper, Verification of Multirate Systems with Multiple Digital Blocks, authored by Arkadiusz Golec, Aldec R&D Engineer and Technologist.

This paper outlines how COMRATE engine can help with the challenge of simulating multirate system-level designs with multiple digital blocks. It contains  practical examples with negative simulation delta time and presentation of relative time domains in traditional timing waveform. The paper also explains how SystemVue/Riviera-PRO users are able to take their designs from concept to hardware faster, using the co-simulation flow to verify the digital hardware portions directly inside the system-level environment.

For more on the Aldec/Agilent co-simulation interface, visit DSP and RF Co-Simulation Application.




Mariusz Grabowski is an FPGA Design and Verification Engineer at Aldec. He works in the field of verification for DO-254 compliance as well as developing digital processing systems. He is proficient in digital design and verification, using hardware description languages such as Verilog/SystemVerilog and VHDL, and the use of verification methodologies such as UVM.

Mariusz is a student at the AGH University of Science and Technology in Krakow, Poland. He also gains practical experience in the AVADER Scientific Group (where he designs novel vision systems on FPGAs) and in the Integra Scientific Group (where he acquires knowledge about microprocessor systems and electronics).


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