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millions, or even billions, of test cycles to completely verify functionality for the average ASIC design. Adding to the challenge, new methodologies must be developed for combined teams of hardware and software engineers to verify both parts of the system function correctly upon integration. These verification concerns are particularly troublesome for companies competing in industries with short time-to-market periods, such as consumer electronics.

 

Hardware/Software co-verification is the process of verifying that RTL code functions correctly in hardware before the design is committed to fabrication. If bugs are determined to exist in post-silicon production, costly re-spins can ultimately reduce profit margin. Hardware-assisted verification platforms provide users with a solution at all stages of the design cycle with a full range of verification capabilities:

• Block level: Designers can decrease test time of systems which require many cycles, by offloading the DUT onto hardware while the simulation is controlled by the HDL simulator. This verification method combines benefits of HDL simulation (signal visibility) and prototyping (speed).
• Transaction level: Emulation at the chip-level can provide up to 10x greater speed that simulation acceleration, allowing up to 100x faster than typical RTL simulation. In this mode the entire DUT and synthesizable portions of the test bench are partitioned and implemented onto the FPGA to obtain MHz emulation speed with debugging capabilities of a simulator. With source level software debugging, static and dynamic probes, users can attain 100% visibility of their design.
• System-level: Verification with prototyping hardware can assess how a system reacts with various data streams (image, video, etc). Users connect IO interfaces such as HDMI, USB, Wi-Fi, and Bluetooth to the system and observe system level behavior. This environment provides the fastest speed, allowing users to verify functionality in a real-time environment.

 

Through each of the stages designers require debugging capabilities to provide an oversight of signals while the system is operating. This becomes especially important when debugging large systems, many of which have multiple levels of circuit design.

 

ASIC/SoC Project Timeline, with and without Hardware/Software co-verification.

In Without co-verification, in Figure 1 the hardware team begins the design process, generating the necessary RTL code, implementing IP cores, and utilizing vendor-specific primitives. Following shortly behind, in parallel, the software team begins generating C/C++ code, operating systems, and software application/drivers. The software teams must then wait for the silicon to be fabricated before testing the software on the hardware board. This pausing of Hardware/Software integration while silicon is fabricated is a clear disadvantage if errors exist when integrating the two portions of the system.

 

With co-verification, in Figure 2 both hardware and software teams begin integration as soon as stable RTL and software code is available. Both teams can also progress together concurrently, improving performance and resolving issues prior to silicon tape-out, saving cost from silicon re-spins.

 

The Solution

The HES-7™ ASIC/SoC prototyping board is part of Aldec's Hardware Emulation Solution (HES™) ecosystem which enables users to utilize their prototyping board for hardware-assisted verification without purchasing any additional hardware. HES-DVM™ (Design Verification Manager) enables multiple modes of verification including: acceleration, emulation, prototyping, and virtual modeling to provide users flexibility in verification and debugging at all stages of the design cycle. HES-DVM also integrates ASIC to FPGA conversion tools (clock conversion, memory mapping, partitioning, etc) with many debugging capabilities such as static probes, dynamic probes, memory visibility, black box modules, and mirror-box modules. With design capacity of up to 24 million ASIC gates, HES-7 and HES-DVM are able to handle the demand of large ASIC/SoC designs while meeting the needs of design verification teams. Learn more.

by the speed of the simulator. In hardware, designers can take advantage of the higher clock frequency, real-world stimulus, but are bogged down by the task oftracing bugs in the code without sufficient information of what is occurring during system operation. Hardware emulators that utilize multiple modes of verification (acceleration, emulation, and prototyping) can provide designers the speed and debug tools required for today's SoC designs at all stages of development.

 

During SoC development, designers require different debugging capabilities at each level of the design. Hardware designers working primarily with RTL code can leverage simulation acceleration as it concentrates on the bit-level. For higher levels of the design, RTL modules are connected to the rest of the SoC using transaction level modeling or virtual platform. System architects or verification engineers would see greater benefit here if they were to employ a higher abstraction layer based on transactions.

 

In the design phase, hardware engineers working within an RTL environment handle numerous HDL files, each with multiple layers of hierarchy. They also integrate multiple IP cores, processors, memory modules, and peripherals into the SoC. Designers on this level have certain debugging requirements to test the integration of all these modules within a hardware platform. They must be able to trace signals both in the simulator as well as in hardware to verify that the system in functioning correctly.

 

HES-DVM™ from Aldec provides multiple debugging capabilities which allow designers to work in a bit-level environment, accelerating the time required to find and solve issues:

• Static Probes allow users to specify design internal signals for debugging in the HDL design. This specification will be available in the simulator and can be observed directly in a waveform viewer;
• Black Box Signals exclude design structures from hardware in order to simulate them in an HDL simulator. This is helpful when non-synthesizable constructs are buried deep in the design hierarchy;
• Mirror Box Signals are not excluded from hardware, but are mirrored in HDL simulation. This is particularly helpful where hardware models behave differently from HDL simulation.

In the verification phase, system architects and verification teams continue to require a higher level overview of the system to validate that all portions of the SoC work together correctly. Once again, this can be accomplished using transaction level modeling or virtual platforms. For this stage of development software designers will continue to have their own set of debugging requirements and may require accessing memory to verify correct values, checking values of process registers, or setting up signal triggers for logic analyzers. Verification teams may also need to use test sequences written in other languages other than Verilog/VHDL, which may be C, C++, SystemC, or SystemVerilog.

 

HES-DVM™ addresses these verification requirements by leveraging:

• Dynamic debugging to deliver configurable access to any register in the system design;
• Hardware-based Visibility Debug (Figure 2) to analyze design RTL sources to identify the minimum number of debugging probes that must be present in the emulation hardware to guarantee 100% debug visibility;
• Memory Debugging to allow viewing contents of all memory mapped instances in HES-DVM. This enables changing of contents of a single memory cell or an entire block and saving and loading memory contents to and from a source file; and
• Advanced Logic Analyzer, a debugging tool capable of 16 separate trigger ports, each having a maximum width of 256 bits.

HES-DVM provides numerous debugging capabilities for different modes of verification, allowing SoC designers to take advantage of the rich debugging environment of RTL simulation with the speed of hardware implementation. As ASIC’s and SoC's continue to grow larger and more complex, the HES ecosystem continues to meet the needs of design and verification teams. Learn more.