Aldec Serves up Emulation and Static Design Rule Check Solutions at 10th annual ARM TechCon Conference

Date: 2014/09/29
Type: Release

Henderson, NV – September 29, 2014 – Aldec, Inc., a pioneer in mixed HDL language simulation and hardware-assisted verification solutions for system and ASIC designs, will be on hand at the 10th annual ARM TechCon Conference, October 1-3, 2014 in Santa Clara, CA.

As a member of the ARM Connected Community, Aldec provides a comprehensive hardware design and verification platform for Emulation, Prototyping, Design Entry, HDL Simulation, and Design Rule Checking.

Visit Aldec at ARM TechCon Booth #712 to learn more.


HES™ FPGA-based emulation incorporates standard co-emulation interface SCE-MI with TLM wrappers used for seamless integration with virtual platforms like ARM® Fast Models or OVP™. Emulation connected with virtual platform makes an ideal software development environment with early access to complete SoC model without slow RTL simulation.  Library of emulation proof VIPs (Verification IP) containing AMBA AHB and AXI transactors assures fast emulation bring-up.



HES-7™ for ARM® Cortex®-A9 based design integration; added peripherals and memories for complete System-on-    Chip prototyping platform.


Static Design Rule Checking

ALINT™ addresses issues early in the design cycle with advanced check for the structural CDC issues and extensive coverage of design rules based on recommended industry standards.


ARM® TechCon™ Where Intelligence Connects™ - learn more

Santa Clara Convention Center October 1-3, 2014

ARM TechCon’s unique 360-degree interactive training ground is seeded to connect, instruct, advise and enable the world of electronic and ARM-based computer design.

ARM TechCon Expo (Booth 712)

Wednesday, October 1           11:00 am to 6:00 pm 

Thursday, October 2               10:30 am to 5:30 pm

ARM TechCon Booth Crawl – Drinks, Games (Booth 712)

Wednesday, October 1           4:00 pm to 5:30 pm


About Aldec

Aldec Inc., headquartered in Henderson, Nevada, is an industry leader in Electronic Design Verification and offers a patented technology suite including: RTL Design, RTL Simulators, Hardware-Assisted Verification, SoC and ASIC Prototyping, Design Rule Checking, IP Cores, Requirements Lifecycle Management, DO-254 Functional Verification and Military/Aerospace solutions.


Aldec is a registered trademark of Aldec, Inc. All other trademarks or registered trademarks are the property of their respective owners.

Media Contact: Aldec, Inc.                               
Christina Toole, Corporate Marketing Manager
+ (702) 990-4400
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