Push the UVM Start Button then Hit the Accelerator

by Doug Amos

So, you’re STILL not using UVM? Maybe you’ve taken a good look and decided that the Universal Verification Methodology for SystemVerilog (UVM) is not for your team. Maybe, you’ve not got round to taking that close look, but you’ve read a lot of these kinds of articles and been scared off by the warnings that UVM is hard to learn. This article won’t help you learn ANY of it, but it will point you to how you might speed up your UVM learning, your UVM adoption and even your UVM execution throughput.

After all, who needs a steep learning curve on top of all that other verification work? Then there is the uncertainty of the potential return on investment in adopting UVM. Will it really find more bugs or verify your design faster?

For the rest of this article, visit EDN Europe.