SemiWiki: Up front phases improve CDC analysis

Date: 2016/09/19
Type: In the News

By Don Dingee

Many tools find clock domain crossings (CDCs) in FPGA designs. Some don’t find the right ones since they don’t comprehend things like in-house synchronizer constructs. Some find too many based on misunderstanding intent, inaccurate constraints, and other factors that lead to noise. A new Aldec webinar offers guidance to improve CDC results.

Sergei Zaychenko of Aldec offers one diagram as a refresher on how CDCs create metastability, and the variables that factor into MTBF. His “impossible to avoid” comment – if there are multiple clock domains, there are CDCs by definition – suggests the urgency of finding and mitigating CDCs in an FPGA design.

For the rest of this article, visit SemiWiki.

Ask Us a Question
x
Ask Us a Question
x
Captcha ImageReload Captcha
Incorrect data entered.
Thank you! Your question has been submitted. Please allow 1-3 business days for someone to respond to your question.
Internal error occurred. Your question was not submitted. Please contact us using Feedback form.
We use cookies to ensure we give you the best user experience and to provide you with content we believe will be of relevance to you. If you continue to use our site, you consent to our use of cookies. A detailed overview on the use of cookies and other website information is located in our Privacy Policy.