Pick & Place - Embedded Vision & uARM Robot Control - reference design based on TySOM EDK. The demo shows a robotic arm representing an IoT actuator controlled from TySOM board and performing pick & place operation. The uARM is additionally equipped with USB camera for objects recognition so that the robot can recognize the objects and sort them according to the recognized pattern.

IoT Gateway with Amazon AWS - reference design based on TySOM EDK that shows TySOM board used as the IoT gateway for multiple sensors using various wreless or wired communication protocols. The IoT gateway device runs an embedded Linux and implements MQTT protocol to connect with the Amazon AWS IoT cloud service to transfer preprocessed and encrypted from sensors to the Amazon IoT Cloud service. The end user can connect to the same cloud service in order to check, control and supervise all IoT nodes and gateways that can be spread worldwide.

Object Movement Detection reference design based on ViBe™ Background Subtraction algorithm and HES-HPC™ FPGA-based Accelerator running @1920x1080, 30fps. The image processing background subtraction techniques are utilized to transform and detect moving objects in recorded video. HES-HPC™ platform provides performance enhancement by utilizing extreme parallel processing capabilities of FPGAs to execute computationally intensive image transformations.

Genome Short Reads Alignment Aldec to present AccuRA™, a high-performance reconfigurable FPGA accelerator engine for ReneGENE™, offered on Aldec HES-HPC™ for accurate, and ultra-fast big data mapping and alignment of DNA short-reads from the NGS platforms. AccuRA demonstrates a speedup of over ~ 1500+ x compared to standard heuristic aligners in the market like BFAST which was run on an 8-core 3.5 GHz AMD® FX™ processor with a system memory of 16 GB. AccuRA employs a scalable and massively parallel computing and data pipeline, which achieves short read mapping in minimum deterministic time. It offers full alignment coverage of the genome (million to billion bases long), including repeat regions and multi-read alignments

  FPGA Prototyping and Emulation are converging very closely nowadays with Aldec pioneering and remaining on the cutting edge in this field with HES™ Hardware Emulation Solutions. The maturity of FPGA technology and accumulated experience of FPGA board designers and EDA software developers at Aldec enabled the combined emulation and prototyping techniques that had not been previously available. During DAC 2017 Aldec will present the newest HES achievements in both emulation and prototyping that bring up the technology and user experience to the next level. The following new products will be showcased:

HES Cloud - Emulation service in the Amazon AWS Cloud Aldec will announce the availability of the HES Cloud service where emulation hardware and software HES-DVM along with Riviera-PRO simulator are available remotely in the Amazon AWS Cloud. With the HES Cloud, the FPGA based emulation will now be more easily accessible as the ownership cost barrier is being removed. The end user can lease the high end emulation product for the time of design verification or pre-silicon software bring up and use it for simulation acceleration or transaction level emulation with the interfaces and infrastructure based on Accellera SCE-MI (Standard Co-Emulation Modeling Interface). We will demonstrate the UVM simulation acceleration of the Network-On-Chip (NoC) design that runs in the HES Cloud.

HES-DVM Physical Prototyping mode Multi-FPGA physical prototyping has always been a challenge due to complicated process of design partitioning with limited number of inter-FPGA connections and several constraints regarding design clocking in FPGA. Aldec will present a new HES-DVM Physical Prototyping mode that automates design compilation and partitioning on boards with multiple FPGA. The new user interface provides following features to achieve the highest clocks frequency: * guided partitioning with impact analysis of different partition assignments * controlling allocation of FPGA resources and interconnections * configuring several I/O multiplexing options including SERDES and LVDS signalling * critical path analysis * generating FPGA chip wrappers and initial design aware constraints The HES-DVM Physical Prototyping mode significantly shortens time of design setup for multi-FPGA prototyping from months to weeks and allows achieving a reliable prototype build runing at higher MHz rates than one prepared with traditional methods or other tools.

Hybrid co-emulation with QEMU A reliable Hardware/Software co-verification technique is indispensable for SoC ASIC verification and validation. QEMU is a generic and open source machine emulator that supports various computer hardware architectures including ARM® Cortex® families. It can be connected with the Aldec HES-DVM™ emulation platform to provide a complete hybrid co-emulation environment for SoC ASIC designs. We will demonstrate the latest QEMU Bridge designed to provide connection between QEMU emulating the ARM Cortex processor subsystem and other hardware modules with AMBA AXI interface that run in the HES FPGA board.

ADAS Multi-Camera Surround View reference design based on TySOM-2-7Z045 EDK + FMC-ADAS + FMC-Vision. The reference design captures, processes and displays 4 simultaneous First Sensor® Blue Eagle™ camera video streams in real-time. In order to achieve the goal for real-time processing performance, the most computational intensive parts of the code are off-loaded from ARM Cortex-A9 to FPGA part of Zynq device using Xilinx SDSoC™ tool. The accelerated part includes edge detection, colorspace conversion and frame merging tasks.

Face detection / Driver drowsiness detection reference design based on TySOM-2 EDK + FMC-Vision. The reference design captures and processes camera video stream in real-time. The driver's face is detected and its movement and eye blinking are monitored for drowsiness detection. In order to achieve the goal for real-time processing performance, the most computational intensive parts of the code are off-loaded from ARM Cortex-A9 to FPGA part of Zynq device using Xilinx SDSoC™ tool. The accelerated part includes edge detection, colorspace conversion and frame merging tasks.

Regression testing is one of the most important aspects of a modern verification environment. However the creation of such an environment may be challenging. Test suite sources need to be versioned and correlated with the corresponding project revision. Retest should be done only for tests which cover the difference between revisions. Finally, collected metrics should be connected with all the above mentioned revisions. The demo will present Riviera-PRO in batch mode using open-source Jenkins-Github tool collaboration. Jenkins is a Continuous Integration Software. Together with GITHUB and Riviera-PRO Metric-Driven Verification Methodology, based on Verification Plan, Aldec provides a powerful solution for regression testing. We will present step by step how to create a complete environment to get your design retested and documented.

Traditional design rule checking (DRC) approach can catch a broad class of RTL coding mistakes, but it's generally limited to detecting the misused combinations of language constructs or the undesired netlist patterns. Sometimes a purely static approach is not enough to give a final judgment on the issue relevance, and the DRC tool could become either too optimistic (might miss an important mistake) or too pessimistic (be noisy). For certain classes of mistakes the DRC methodology needs to be extended with additional functional verification methods. The examples include array access boundaries, full_case/parallel_case tables, X-assignments, conflicting drivers. DRCs tool can still detect suspicious patterns, but instead of flagging them as errors immediately, one or more assertions could be auto-generated and analyzed during the simulation or using an external formal verification tool. Another reasonable application of the assertions-based functional checks are restrictions on the use of CDC synchronization protocols, which enrich ALINT-PRO CDC output with proven assumptions on how the synchronizers are supposed to be controlled.

SystemVerilog has proven to be successful as a unified language both for logic design and verification. Major synthesis tools already support new SystemVerilog RTL constructs that better clarify the designer's intent and improve the efficiency of engineering efforts. Of course, using new SystemVerilog constructs to describe custom RTL blocks immediately introduces additional classes of RTL coding mistakes. The areas of typical coding issues include 2-valued vs 4-valued data, user-defined types, new kinds of processes and conditional statements, new expressions, and advanced constructs to descrbie re-usable design hierarchies. Frequently repeating mistakes create an interest in SystemVerilog-specific linting rules, and this is where Aldec ALINT-PRO tool comes in. This presentation discusses a number of frequent SystemVerilog design issues, which could be caught with the latest Aldec linting solution.

Today's FPGA SoC embedded designs present new verification challenges for both software and hardware engineers. The common issues are related to HW/SW integration, and they are typically found in the testbed with the FPGA running. Finding the issues in the the FPGA testbed is often too late and can cause project delays. Aldec provides a HW/SW co-simulation approach based on open-source QEMU. System integration and simulation of FPGA custom IPs with open-source QEMU is now simplified with the addition of Aldec QEMU Bridge that connects QEMU and Riviera-PRO. The QEMU Bridge converts SystemC TLM transactions to AXI and vice versa providing a fast interface for co-simulation. In this presentation and demo we will show co-simulation of RTL design together with software/firmware running on ARM ZynQ virtual platform in QEMU. Such a solution helps software teams to develop Linux-based software or firmware concurrently with hardware development. The solution may be used also by hardware developers to run software driven testbench and for HW/SW debugging.

Aldec and Silvaco will proudly introduce mixed-signal co-simulation interface based on high-performance tools Riviera-PRO Advanced Verification Platform and SmartSpice Parallel SPICE Circuit Simulator. Together Aldec and Silvaco teams will present their respective state-of-the-art technologies for the digital and analog domains. Now with the co-simulation interface, we are joining the capabilities of both tools to deliver a robust solution for mixed-signal designs. The demo will show parsing of a mixed-signal design, compilation, elaboration and mixed-signal simulation. We will show how the digital and analog domains can communicate and how a user can obtain results of Verilog-A/SPICE and Verilog-D co-simulation in Riviera-PRO user interface. Users can view the co-simulation results using Riviera-PRO Advanced Waveform Viewer and debug using Riviera-PRO debugging features.

Late discovery of requirement errors in the project cycle is very expensive to fix. Requirement changes are common and they are expected to happen on any given project. Microsoft® Office™ tools such as Word and Excel do not facilitate the required environment for managing constantly changing requirements because they impede collaboration, do not provide requirement versions comparison and lack the required traceability automation and precision. During this technical session we will present and analyze the limitations of Office tools that disqualify them from the professional requirements management process. At the same time we will show you how these limitations are addressed in Spec-TRACER and how to use the professional Requirements Management tool to help streamline your organization’s processes and get better production in shorter time.