SemiWiki: RDC - A Cousin To CDC

by Alex Tan

In a post-silicon bringup, it is customary to bring the design into a known state prior to applying further testing sequences. This is achieved through a Power-on-Reset (POR) or similar reset strategy which translates to initializing all the storage elements to a known state.

During design implementation, varying degrees of constraining may be applied on the Reset signal. For example, designer may impose some multicycle paths (MCP) constraint in order to avoid unneeded timing optimization on the reset logic (although check for slew violation is still necessary). In this article we will discuss Reset mechanism and RDC (Reset Domain Crossings).

Just like the notion of hard- or soft-reboot in system bringup, we could first categorize this initialization step into hard/soft-reset as captured in figure 1.

In synchronous designs, asynchronous reset de-assertion operation causes metastability issue and unpredictable values in the memory elements. This increases risk of not having a stable design initialization. The snapshot in figure 2 illustrates the issue, in which the reset signal de-asserts during the active clock edge change --causing metastability issues as well as randomly initialized register values. To avoid a non-determinism, synchronization at reset deassertion is needed.

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