HES7XV12000BP Prototyping and Emulation Main Board

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Aldec’s large capacity board that features Xilinx Virtex-7 FPGA technology contains six XC7V2000T logic modules and is the most advanced in the market one piece PCB prototyping board of Virtex-7 family. It is targeted to high speed physical prototyping and emulation of complex ASIC and SoC designs. The board provides estimated capacity of 72 Million gates and is easily extendable via backplane and daughter card non-proprietary connectors (BPX & FMC). Two of six Virtex-7 FPGA modules are connected with four DDR3 SO-DIMM slots to support up to 32 GB of aggregated memory. Larger capacity of 288 Million gates can be achieved with four HES7XV12000BP boards connected in the backplane board HES7BPX4. Highest I/O count packages of Virtex-7 devices and proper on-board traces routing assure reliable LVDS and GTX transfers up to the device inherent limits.


Very precisely designed clocking block provides 5 global clock lines routed to each FPGA device. It provides multiple configuration options due to integrating different oscillators, programmable clock synthesizers and crosspoint switch multiplexers. The global clock network can be also driven from external sources via dedicated SMA connectors as well as from backplane and daughter card sockets. The global clock network is based on LVDS signalling to assure high level of signals integrity and immunity to distractions. Complementary to global clocks there are separate clock oscillators dedicated to GTX links and DDR memories.

Hosting & Interfaces

The board configuration and monitoring controller is preloaded in a dedicated FPGA (Spartan-6) and provides USB based interface that is used by Hes.Asic.Proto board configuration and management software available on Linux and Windows host PC. Additional Virtex-7 FPGA can be used as a host bridge with standard interfaces like PCIe x8 Gen3, USB 3.0, QSFP+ and SATA. Ready to use, PCIe host controller is preloaded in Virtex-7 FPGA and the corresponding HES PCIe driver is included. Usage of this host controller is facilitated due to Proto-AXI interface module IP that is based on AMBA AXI standard and accompanying high abstraction level C++ API.

Besides physical prototyping this board can be reused for HES emulation applications like simulation acceleration or co-emulation with virtual models.

HES7XV12000BP Prototyping and Emulation Main Board

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FPGA & Capacity

  • Main FPGA: 6 Virtex-7 XC7V2000T (FLG1925 - 1200 I/O, 16 GTX)
    • ASIC Gates estimated for 60% of FPGA utilization
      • 72 Million Gates single board
      • 288 Million Gates with four boards in a backplane
  • Host FPGA: Virtex-7 XC7VX690T (FFG1926)
  • Debug FPGA: Spartan-6 XC7K325T (FFG900)

Flexible Clocking

  • Flexible global clock network connected to each of Virtex-7 FPGA
    • 5 global, low-skew, clock lines with fanout buffers
    • Configurable with PLLs & Crosspoint switch muxes.
      • Precision any-frequency clock synthesizer (Si5326)
      • LVDS crosspoint switch (DS10CP154A)
    • On-board LVDS clock sources
      • Oscillators: 192, 250, 300, 400, 500 MHz
    • External clock sources
      • 5 clocks from dedicated FMC connector
      • 4 clocks from backplane connector
      • 6 clocks from pair of SMA connectors
  • 1 global reference clock connected to all FPGAs (fixed at 200 MHz)
  • GTX reference clocks
    • 4 dedicated GTX oscillators (2x 200 MHz, 2x 156.25 MHz)
    • External from SMA connectors
    • Routed through fanout buffers to all Virtex-7 FPGA (SY89468U)
  • Separate reference oscillators for each DDR (fixed at 200MHz)
  • Dedicated external clock connectors: SMA & FMC (input & output)
  • 170 clock I/O of all Virtex-7 FPGAs available on connectors
    • 60 DIFF clock lines on backplane connector
    • 110 DIFF clock lines on FMC daughter card connectors

Connectivity & Expandability

  • Full size BPX backplane connector
    • High speed (25 Gbps) connectors: MOLEX 76150 series
    • Backplane to Virtex-7 aggregated connections
      • 720 I/O (360 DIFF) - standard GPIO optimized for LVDS & TDM
      • 12 GTX - high speed serial I/O
  • Daughter card connectors (FMC-HPC)
    • Standard FPGA Mezzanine Card connectors
      • Compliant with ANSI/VITA 57.1 FMC Standard
      • 9 FMC-HPC sockets connected to Virtex-7 FPGAs
    • FMC to Virtex-7 aggregated connections
      • 1296 I/O (648 DIFF) - standard GPIO optimized for LVDS
      • 16 GTX - high speed serial I/O
  • Inter-FPGA aggregated connections
    • Main FPGA interconnections
      • 2036 I/O (977 DIFF) - standard GPIO optimized for LVDS & TDM
      • 43 GTX - high speed serial I/O
    • Main to Host FPGA connections
      • 200 I/O (96 DIFF) - standard GPIO optimized for LVDS
      • 18 GTX high speed serial I/O
    • 89 I/O common/debug bus
    • 3 I/O common lines

Memory Resources

  • Up to 32 GB of DDR3 available for main FPGAs
    • 4 DDR3 SO-DIMM slots connected to 2 of main Virtex-7 FPGAs
    • 2 slots and up to 16 GB per FPGA
  • Memories connected to host FPGA
    • DDR3 SO-DIMM slots (up to 16 GB)
    • SPI Flash, NAND Flash
  • Board configuration memories
    • Micro-SD card slot
    • 2x SPI Flash

Interfaces & Hosting

  • Host interfaces at Virtex-7
    • 2x PCIe
      • Fixed PCIe x8 gen3
      • Configurable PCIe x16 / x8 gen3
    • 4x SATA
    • Gb Ethernet
    • QSFP+
    • USB 3.0 Device
    • UART/USB
  • Board configuration and FPGA programming
    • Aldec’s Board Configuration Controller loaded in Spartan-6 FPGA
    • Programming from Host
      • via USB 2.0 (Aldec Hes.Asic.Proto application)
      • via JTAG (Xilinx utilities)
    • Programming from Micro-SD card
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