Deleting Design files


Which files in an Active-HDL design or project can be deleted to save space?


A design is stored in a folder whose name is usually the same as the design name. The content of its subfolders are as follows:

• \compile

Temporary and intermediate file - among others, VHDL, Verilog, and EDIF files generated from block and state diagrams.

• \implement

The files produced by the implementation tool used to process the design.

• \log

Console log files.

• \slp

Contains the slp_model.dll dynamically-linked library and intermediate files generated by SLP; the directory is created when simulation is initialized with SLP acceleration enabled.

• \src

Design source files and other resource files displayed on the Files tab of Design Browser.

• \synthesis

The files produced by the synthesis tool employed to process the design.

• \_synthesis

Post-synthesis library files.

• \_timing

Timing library files.

Files residing directly in the design folder:

.adf is the design description file.

.aws is the workspace description file.

Edfmap.ini:- to enable simulation of EDIF netlists generated by different tools, Active-HDL allows remapping of cell names, pin names, and library names appearing in primitive cell instantiations. Such a remapping allows using a reduced set of universal primitive libraries and is performed automatically during compilation of netlist files. The description of the remapping rules resides in the Edfmap.ini.

compililation.order:- It contains compilation order of files and is also the default synthesis order if the synthesis order (synthesis.order)is not specified.

.wsp stores information on the current layout of the Active-HDL framework window.

.lib and *.mgf files store the default working library of the design.

compile.cfg, fsm.set, and bde.set are additional block/state diagram configuration files.

To copy a design manually, you must copy the entire design folder. Keep in mind, that designs may include links to files stored outside their design folders.

However we recommend adding everything from src folder and all files under design folder except *.mgf ,*.cfg and *.lib files. You do not need to add anything to compile or log sub folders.

When you run your design, you will need to recompile your design files prior to running simulation.

You can pack and save the current design or the entire workspace with all its designs in a ZIP-format archive file. So created archive file can contain a customized set of items added to the "root" including files and subfolders. Long file names are preserved. To unzip such an archive file, you can use any extracting program that accepts the ZIP format.

To archive the current workspace/design, choose Archive Workspace or Archive Design from the Workspace or Design menu, respectively and follow instructions of Archive Workspace/Design Wizard .

For details on Archive Workspace/Design Wizard dialog boxes, see the Specifying the Archive File Settings, Specifying the Contents of the Archive, and Creating the Archive topics, respectively.

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