White Papers

The Federal Aviation Administration (FAA) recognizes the use of commonly used tools for FPGA design and verification such as RTL Simulator, Synthesis, Place & Route and Static Timing Analysis. For DAL A and B FPGAs, the FAA also recognizes other tools that improve design, verification, traceability and project management including Requirements Management, Traceability, Tests Management, Design Rule Checker, Clock Domain Crossings (CDC) Analysis, Code Coverage and FPGA Physical Test Systems.

Abstract: Aldec's Server Farm Manager (SFM) addresses ASIC regression testing issues for the fast, cost effective and high quality ASIC design verification.

Abstract: Engineers working on modern, large FPGA designs face multiple challenges: changing languages, methodologies and tools implementing them. The fact that many designs now contain both hardware and software only adds to the confusion. This document tries to clarify the situation.

The increasing adoption of large, high-pin-count and high-speed FPGA devices means that right-first-time printed circuit board (PCB) design practices are more essential than ever for ensuring correct system operation. Typically, the PCB design takes place concurrently with the design and programming of the FPGA. Signal and pin assignments are initially made by the FPGA designer, and the board designer must correctly transfer these assignments to the symbols used in their system circuit schematics and board layout. As the board design progresses, pin reassignments may be needed to optimize the PCB layout. These reassignments must in turn be relayed back to the FPGA designer so that the new assignments can be processed through updated placement and routing of the FPGA design. To overcome these challenges, Zuken and Aldec provide an integrated design environment to support these design flows.

Abstract: As the number of mobile and personal applications grows, usage of embedded processors becomes a necessity. New FPGA devices with so called soft or hard processor cores enable fast migration from the FPGA-only to the SoC applications and projects. This affects not only the hardware alone, but also the tools supporting the latest FPGA devices for SoC designers. Such tools are discussed within this document.

Abstract: PSL (Property Specification Language) is the easiest introduction to the world of design properties, assertions and coverage points to anybody familiar with VHDL (VHSIC Hardware Description Language). The designer of a digital circuit has the best understanding of the operation of the circuit, which makes her or him the best person to define properties that will fire assertion messages in case of incorrect design behavior during simulation or provide valuable feedback to the testbench creator by showing that all desired behaviors were covered during verification. For this reason, the use of embedded PSL properties and assertions is highly beneficial to the engineers and makes their designs better.

Abstract: PSL (Property Specification Language) is one of the easiest introductions to the world of design properties, assertions and coverage points to anybody familiar with Verilog HDL. The designer of a digital circuit has the best understanding of the operation of the circuit, which makes her or him the best person to define properties that will fire assertion messages in case of incorrect design behavior during simulation or provide valuable feedback to the testbench creator by showing that all desired behaviors were covered during verification. For this reason, the use of embedded PSL properties and assertions is highly beneficial to the engineers and makes their designs better.

Abstract: SVA (SystemVerilog Assertions) language is one of the easiest introductions to the world of design properties, assertions and coverage points to anybody familiar with Verilog HDL. The designer of a digital circuit has the best understanding of the operation of the circuit, which makes her or him the best person to define properties that will fire assertion messages in case of incorrect design behavior during simulation or provide valuable feedback to the testbench creator by showing that all desired behaviors were covered during verification. For this reason, the use of SVA properties and assertions directly in the design code is highly beneficial to the engineers and makes their designs better.

Abstract: This paper presents a new approach in domain of high level digital circuits simulation and modeling that benefits from high level mathematical environment delivered by MATLAB. It allows to integrate design process and directly verify obtained results with mathematical formulas or complex operations that are not available in standard HDL languages. A part of HDL code can be placed for verification purposes inside the advanced mathematical model or can execute complex calculation. Paper presents problems that are introduced by hybrid simulation and modeling environment concerning data representation, simulation process and optimal performance.

Abstract: This paper describes the theoretical background, current status and future challenges facing interoperable cryptosystem for safe delivery of Intellectual Property (IP) to be used in VHDL and SystemVerilog design and verification. The system must be reliable, and interoperable, i.e. enable safe use of IP source in a variety of tools. IEEE P1735 Working Group currently develops proposed standard describing such a cryptosystem.

If you are new to DO-254, this white paper can serve as your starting point as you educate yourself with the guidance and regulation. This white paper provides an overview of RTCA/DO-254 purpose, scope and processes, and as well as description of Aldec’s specialized tools for DO-254 targeting DAL A and B PLDs.

シミュレーションと論理合成のミスマッチの問題は、物理デバイスの誤動作を引き起こす可能性があります。RTLシミュレーションで機能的に完璧であっても、物理的な実装で重大なデザインバグが含まれている可能性があります。RTLリントは、シミュレーションと論理合成のミスマッチ問題を特定して修正する唯一の方法です。本紙では、シミュレーションから論理合成への典型的なミスマッチ問題を簡単な例で示します。 記載されている問題ごとに、リントチェックで確認され、説明されます。

Abstract: Modern digital designs reach the scale of complete systems and require support of Constrained Random Test and Functional Coverage in verification. Although VHDL does not have built-in, direct support for those methodologies, there are neat solutions that allow their quick implementation in your testbench.

Abstract: Growing customer requirements and technological abilities increase the design complexity of hardware and software. Time to market is shortening as well as the lifetime of new designs. In order to be able to meet all those requirements a new approach to the design process is required.

Digital circuit designer very frequently faces the dilemma: how to implement arithmetic operations in his or her design. This article presets balanced solutions that provides high level of functionality and maintains decent readability of the code.