Play Webinar

Title: Partitioning Design for Custom or In-house Designed Multi-FPGA Board

Description: Presently, emulation and prototyping are essential verification and validation techniques for a SoC, ASIC, ASSP or large scale FPGA design. The FPGA based prototyping platforms are superior due to their performance and versatile connectivity. However, challenges of the multi-FPGA design setup requiring complex partitioning, I/O interconnections and mapping multiple clock domains across multiple devices drive many away from this platform. Design partitioning assistant software that can be used with either off-the-shelf or even custom made FPGA boards can significantly reduce the risk and time of the prototype bring-up. Aldec HES-DVM™ Prototyping Platform is here to aid in rapid implementation of fast and reliable FPGA prototypes. Design setup for a large multi-FPGA platform is facilitated with the DVM tool that provides partitioning utilities and can convert ASIC clocks to FPGA-proof structures, automate I/O assignment and control the timing critical paths across the board. We will demonstrate the HES-DVM prototyping flow that can be used with custom or in-house designed boards, even before the FPGA board design is finished. The results of preliminary partitioning can provide invaluable feedback to the board design team and a handful of hints on design-specific board improvements.

Signing up for an account is easy. With an Aldec account you'll have easy, one-click access to event registration, support, product downloads, evaluation licenses, recorded webinars, white papers, application notes and other resources. Simply provide your corporate e-mail address below - all account requests are verified and confirmed within 48 hours.

If you already have an Aldec account, please Sign In below to download the file.