Play Webinar

Title: Verifying Finite State Machines with Aldec Products

Description: Finite State Machines play a key role in design functionality being an essential part of design control logic. FSM-related bugs have direct influence on core design functionality, and usually there are no workaround solutions to the FSM-related issues. Therefore, designers have to pay special attention to the correct design and verification of the FSM code. Static FSM verification methods complement functional simulation to achieve flawless FSM functionality. Static code styles and naming conventions checks help designers to develop clear and concise FSM code as well as enforce the company-specific FSM development styles and restrictions. The recently added FSM viewer allows designers to extract and explore FSM structures in existing RTL code for the debugging, back-annotation and documentation purposes.

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