Play Webinar

Title: Using OSVVM’s AXI4 Verification Components (Part 2) Writing Tests and Configuring the AXI4 VCs

Description: This “Getting Started” presentation is for engineers who need to use the OSVVM AXI4 verification components (VCs) in their testbenches. Part 2 of this presentation focuses on how to write tests and configure the AXI4 VCs. AXI4 VCs are probably the most complex VCs in the OSVVM library. This complexity is due to the AXI4 interface having 5 independent interfaces: Write Address, Write Data, Write Response, Read Address, and Read Data. Going further, the interface supports user configurable optional aspects of the interface – such as the ID and User fields. In this presentation we examine the structure of OSVVM test cases, the AXI4 transaction API, how to do byte transfers, how to do burst transfers, how to handle arrays of VCs, how to configure AXI4 VC options, how to randomize delays for xValid or xReady, and how the test case can directly read or write values in the Axi4Memory. As we look at the OSVVM transaction API we will note that it does not specify the byte enables. Instead, OSVVM determines the byte enables by looking at the width of the data and the lower bits of the address. OSVVM’s burst interface is supported by FIFOs that are in the transaction interface. These FIFOs allow any size of std_logic_vector value to be pushed into them. This allows the burst interface to be used in either byte mode or word mode. In byte mode, the burst is a sequence of bytes that are assembled by the VC into interface words. This allows OSVVM to create test cases that are independent of the actual data bus width.

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