Play Webinar

Title: Practical Co-Simulation Techniques with OSVVM Part 2: RISC-V Software and Logic Co-Development

Description:

OSVVM is a powerful open-source VHDL verification methodology and library widely adopted for FPGA and SoC verification. It provides a comprehensive set of capabilities including transaction-based verification, constrained randomization, functional coverage, scoreboards, memory models, reusable testbench architectures, and advanced scripting support across leading simulators such as Aldec’s Active-HDL and Riviera-PRO.

As embedded software and FPGA logic become increasingly interconnected, verification teams require efficient ways to validate hardware and software together within a unified simulation environment.

In this, the second webinar in our three-part series, we explore how OSVVM co-simulation enables RISC-V software and logic co-development using C/C++ instruction set simulators (ISS). The session demonstrates how software workloads can interact directly with FPGA-based logic simulations to accelerate system-level verification and embedded software validation.

Attendees will learn how to integrate the OSVVM rv32 RISC-V ISS model into an OSVVM verification environment, develop software-driven test scenarios, and build scalable verification flows for embedded applications. The session also includes a live demonstration of co-simulating a RISC-V program using the rv32 ISS within an OSVVM test environment. In addition, the webinar explores future directions for RISC-V support and co-simulation capabilities within the OSVVM ecosystem.

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