Play Webinar

Title: Practical Co-Simulation Techniques with OSVVM Part 3: Introduction to Protocol Verification with Co-Simulation

Description:

OSVVM is a powerful open-source VHDL verification methodology and library widely adopted for FPGA and SoC verification. It provides a comprehensive set of capabilities including transaction-based verification, constrained randomization, functional coverage, scoreboards, memory models, reusable testbench architectures, and advanced scripting support across leading simulators such as Aldec’s Active-HDL and Riviera-PRO.

Modern FPGA and SoC verification increasingly relies on sophisticated protocol models capable of interacting with RTL simulations at both the transaction and software levels. OSVVM co-simulation enables engineers to extend traditional verification component (VC) architectures by integrating native C and C++ models directly into VHDL-based verification environments.

In this, the final webinar in our three-part series, we explore how complex protocol verification components can be constructed using OSVVM co-simulation techniques, using the new PCIe co-simulation VC as a practical case study. The session will examine the architecture and internal design of the PCIe VC, demonstrate how C/C++ protocol models are connected to OSVVM verification environments, and show how similar co-simulation VCs can be developed for other advanced protocols.

Attendees will also see a live demonstration of how the PCIe co-simulation VC can be used to drive and verify Altera Cyclone V Hard IP for PCI Express within an OSVVM testbench using Riviera-PRO.

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