Aldec Verification Tools Implement the ASIC Verification Flow

Aldec has, over the last 30 years, established itself as the preferred provider of high-performance, cost-effective verification tools for use in proving out complex FPGA designs. As the logic capacity and capability of FPGAs have increased, however, the distinction between FPGA and ASIC design has narrowed. A modern FPGA verification flow looks very much like an ASIC verification flow.

Small and large fabless companies alike need a reliable verification partner that suits their budgets while still providing a high level of support. To answer the call, we at Aldec have extended our spectrum of verification tools for use in digital ASIC designs.

A Basic ASIC Verification Flow

Managing verification for ASICs requires a well-defined verification plan.  Efficient verification planning starts with functional and design requirements in which requirements are mapped to verification methods, scenarios, goals and metrics, coverage groups, and results. Mapping entails traceability throughout the project that must be well maintained so that changes in the requirements will seamlessly reflect potential changes downstream to the elements of the verification plan.

While traceability can benefit any design, it is mandatory for safety-critical designs regulated by standards such as ISO-26262 for automotive, IEC-61508 for industrial and DO-254 for avionics.

ASIC design is done almost exclusively at the RTL level. Before functionality is verified, the coding style and structure of the RTL code must be vetted to ensure good code maintainability, to provide for safe synthesis, and to catch potential bugs at the earliest possible stage.

This is the role of linting tools. Such tools use both static and dynamic analysis to ensure that as-written code is of good quality. Certain classes of design – in particular, those intended for safety-critical applications – must adhere to specific coding rules. Such standards include:

• DO-254, a hardware design assurance process for avionics applications;
• The Semiconductor Technology Academic Research Center (STARC), a consortium of 11 major Japanese companies, which has established a well-attested set of rules for coding; and
• The Reuse Methodology Manual (RMM), which contains rules that make code easier to reuse in new designs.

For such designs, linting tools must have access to specific rules libraries against which the design can be verified.

An additional challenge in larger ASIC designs is the prevalence of multiple clock domains. Extra care must be taken to ensure that signals crossing those domains are properly handled. Failure to do so can result in functional and timing failures, or, worse yet, in unreproducible internal metastability. Clock-domain crossing (CDC) tools ensure that signals are properly buffered as they cross from one domain to another.

Once analysis has demonstrated clean code and clocking, then simulation verifies basic functional behaviors across a set of test scenarios. This starts at the unit or module level, where a large number of tests can be run with short simulation run times.

When the individual modules have been integrated into an overall chip design, simulation opportunities may become more limited due to the time it takes to simulate very large circuits across a large number of tests. This is where acceleration can help.

All of the verification acceleration modes involve hardware emulation. An emulator allows the design under test (DUT), as well as synthesizable portions of the testbench, to be implemented in hardware, speeding up execution by hundreds or thousands of times.

The simplest acceleration involves execution at the bit level, but greater speed can be achieved using a SCE-MI interface between the host and emulator. A SCE-MI interface communicates transaction-level, rather than bit-level transactions between the host and emulator. The SCE-MI interface can be used in a number of different verification scenarios, including UVM acceleration and hybrid emulation (or co-verification) using simulation and emulation together.

When timing is critical, at-speed testing of complex design modules can build confidence that the slower-speed simulation and emulation verification haven’t overlooked timing-related bugs. This testing is done once all other bugs have been eliminated, providing greater confidence when the module is integrated into the overall design.

Programmers creating low-level drivers and other code that touches the hardware directly will want to get started coding as early as possible. A virtual platform in conjunction with an emulator is ideal for testing code and SoC level verification in the early stages of hardware design. Once the RTL stabilizes, hardware prototypes enable higher-speed hardware and software testing.

Aldec Verification Tools Implement the ASIC Verification Flow

At Aldec, the tools that we have been developing for years are being extended to address ASIC designs. The following are the key tools, showing how they satisfy the needs of ASIC verification engineers.

When planning the verification, Spec-TRACER™ manages the requirements and verification plans. Spec-TRACER captures all of the verification artifacts needed to ensure that the requirements have been faithfully verified as planned.

Aldec’s ALINT-PRO™ tool provides thorough code analysis as well as CDC verification, supporting both VHDL and Verilog languages. Aldec provides libraries containing well-established criteria for basic coding, CDC, DO-254, STARC, and RMM standards. Code style and correctness are checked using static analysis, done in phases to ensure that individual bugs don’t trigger a cascade of other bugs that would disappear if the initial bug were fixed. The phasing and flow are available out-of-the-box, but they can be customized if desired.

CDC verification starts with static analysis, which checks the network and synchronizer structures. Following that, a testbench is automatically generated for dynamic analysis, with metastability checks, assertion verification, and stimulus coverage analysis.

Riviera-PRO™, Aldec’s flagship simulation tool, picks up after linting is complete. Riviera-PRO is a high-performance simulator that speeds verification through both fast incremental compilation and fast multi-core simulation execution. Riviera-PRO accepts a wide variety of languages, including VHDL, Verilog, SystemVerilog, SystemC, and mixtures of these languages. It can handle the multi-million-gate designs typical of ASIC projects.

Riviera-PRO supports numerous verification scenarios, including UVM, TLM, assertion-based verification, and metric-driven verification based on code and functional coverage. Assertions can be specified as SystemVerilog Assertions (SVA), Property Specification Language (PSL), or OpenVera Assertions (OVA).

Further acceleration can be achieved in conjunction with the HES-7™ hardware platform. HES-7 boards can be used for two different flow elements: emulation and prototyping. The HES-DVM™ tool converts the board into a full-fledged emulator with a SCE-MI 2 interface. HES-DVM provides a complete environment for setting up the design, integrating the design compiler, and debug instrumentation. It can be run through a GUI or by script on Windows and Linux machines.

HES-DVM partitions large designs across multiple HES-7 boards, ensuring that partition boundaries are correctly managed. Individual boards can accommodate as many as 158 million gates each. Current backplanes support 4 boards, but the architecture can be scaled without limit.

HES-DVM supports several host communication schemes for different emulation modes:

• PLI/VHPI for bit-level acceleration
• SCE-MI 2 and DPI-C for function-based transaction-level and UVM verification
• SCE-MI 2 and TLM for macro-based hybrid emulation with a virtual platform running processor models or SystemC testbench
• In-circuit emulation without SCE-MI with speed adapters for external data streams and interfaces

Aldec hardware debugging provides 100% visibility into the design at the RTL level. Debug functions for design signals and bidirectional memory access are available in user interactive Hardware Debugger as well as via C/C++ Debug API for testbench level debug. In addition Aldec provides fast JTAG transactors for attaching software debuggers to a processor in the emulator DUT.

Aldec also provides a custom service to interface HES-DVM to other hardware prototyping platforms, turning them into SCE-MI 2-based emulators.

For at-speed testing, CTS™ provides a platform for high-speed design execution to ensure that there are no lingering high-speed timing bugs.

Finally, a solid collection of verification intellectual property (VIP), including both linting models and simulation models, saves time and ensures that your design receives a thorough checkout.

Industry-Proven ASIC Verification tools

The technology that Aldec brings to ASIC design reflects 30 years of verification development, with an active customer base more than 35,000 strong, over 50 global partners, and a worldwide presence for sales and support.

Aldec supports the full ASIC verification Spectrum through:

• Requirement/specification traceability with Spec-TRACER™
• Static and dynamic code analysis and CDC verification with ALINT-PRO™
• Simulation with Riviera-PRO™
• Emulation with the HES-7™ platform and HES-DVM™ environment
• At-speed module testing with CTS™
• Prototyping with HES-7™ boards
• An extensive VIP library.

The Aldec difference lies in our customer service, our responsive technical support, and in the cost-effectiveness of our tools. For cost-conscious companies of any size that require a high level of support, Aldec becomes the obvious ASIC verification choice.

To learn more about the Aldec ASIC Verification Spectrum, call us at +1-702-990-4400 or email sales@aldec.com.