Datasheet Resources News Training Multimedia FAQ Contact Sales FPGA Test System DO-254/CTS™ is a fully customized hardware and software platform that augments target board testing to increase verification coverage by test and satisfy the verification objectives of DO-254/ED-80. The target design runs at-speed in the target device mounted on the custom daughter board. The simulation testbench is used as test vectors to enable requirements-based testing with 100% FPGA pin-level controllability and visibility necessary to implement normal range and abnormal range tests. The FPGA testing results are captured at-speed and displayed using a simulator waveform viewer for advanced analysis and documentation. Top Features At-speed testing in target device Reuse testbench as test vectors Increase verification coverage by test FPGA I/Os full visibility/controllability Early access to FPGA hardware board for device testing For use with Altera®, Lattice®, Mircrosemi® and Xilinx® devices Supports FPGAs with serial high speed I/Os (ARINC 818, PCIe, DDR3 and LVDS) Single environment to verify all FPGA level requirements Automated in-hardware testing Hardware testing results visualization with waveform viewer Integration with 3rd Party RTL Simulator, Synthesis and P&R Tools CTS Flow Mother Board Daughter Board FeaturedDemonstration VideoDO-254 CTS OverviewRecorded WebinarDO-254 - How to Increase Verification Coverage by Test (Aldec and Altera)DO-254 Requirements TraceabilityManaging Requirements-Based Verification for Safety-Critical FPGAs and SoCsBest Practices for DO-254 Requirements TraceabilityVerification of PCIe-based FPGA Designs Requiring DO-254 ComplianceHow to enforce HDL coding standards and gain the overall design review to meet DO-254 objectivesThe impact of AMC-152A guidance on design and verification process of DO-254 projects ISO-26262 and DO-254 Achieving Compliance to BothTool Qualification – DO-254, DO-330, and ISO 26262 ApproachesManaging DO-254 Compliant DocumentsHow to plan a DO-254 compliant verification process for FPGA designsShortening the verification time of safety critical projectsDesigning Finite State Machines for Safety Critical SystemsCommon Testbench Development for Simulation and PrototypingWhite PaperAldec DO-254 Solutions BlueprintDO-254: Increasing Verification Coverage by Test
