The WHAT is mandatory but the HOW is entirely optional

Intro to High Level Synthesis

Satyam Jani, Product Manager Software Division
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You look confused. Perhaps I owe you an explanation. Anyone familiar with hardware design flow knows that it starts with specification and ends with implementation. The specification in this flow is the “What” – it defines what needs to be designed. The process for implementation is the “How” – it defines how you are going to achieve it.

Let’s break down just one part of the “How” implementation – the Design Process. For many years hand-coded RTL has been used as the de facto method for implementation and it is still being used as predominant method for designing cutting-edge hardware. But does it follow that it is the most efficient method? I would say probably not, especially given the ever-growing complexity of the hardware.

The biggest challenge is that hand-coded RTL is too detailed and complex for today’s standards. This method involves managing a vast amount of detail in technology, clocks, hierarchies, processes, etc. while designing the hardware. This increased level of complexity and numerous details in the code tends to make this method more error-prone as well. It is no secret that a tremendous amount of time is then spent on verification of the hardware.

Is there an option to hand-coded RTL? Is it possible to focus only on design behavior not implementation details? Yes. High-Level Synthesis makes this entirely possible. In fact, this methodology has been on the market for decades and many companies have used it successfully to produce commercial chips. High-level synthesis allows designers to describe hardware at abstraction level which is much shorter and less detailed. Actual focus is always given to create design behavior using high-level models and not on implementation details which reduce design time significantly. These high-level models then are fed to HLS tool to generate high quality RTL.

So you see, the ‘how’ IS entirely optional. There is a better way.

To learn more about high-level synthesis and its benefits, view Recorded Webinar: CyberWorkBench: C-based High Level Synthesis and Verification.


Satyam manages Aldec’s leading FPGA design entry and simulation tool – Active-HDL. He received his B.S. in Electronics Engineering from Sardar Patel University, India in 2003 and M.S in Electrical Engineering from NJIT, New Jersey in 2005.  His practical engineering experience includes areas in Solid state electronics, Digital Designing and functional verification. He has worked in wide range of engineering positions that include FPGA Design Engineer, Applications Engineer and Product Manager.


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