1.1 Basics : Workspace

A Workspace consists of individual designs containing resources such as source files and output files with simulation results. Learn how to create a new Workspace using the New Workspace Wizard, manage an existing Workspace, and manage the different components of the Workspace.

1.2 Basics: Design Flow Manager

In this video, you will learn how to enable the DFM, choose third party vendor tools for synthesis and implementation, and how to access each stage of the synthesis and implementation processes.

1.3 Basics: Library Manager

Learn how to create and manage user libraries, and how to utilize pre-compiled FPGA vendor libraries.

2.1 Design Entry: Block Diagram Editor

In this video we will take a close look at some essential block diagram editor features that will help you design your BDE file much more easily and smoothly.

2.2 Design Entry: FSM Editor

This video will demonstrate how to use the State Diagram Wizard and various other features of the editor such as adding states and converting the graphical model into HDL code.

2.3 Design Entry: HDL Editor

Active-HDL’s HDL Editor is a text editor for editing HDL source code. This video will show how to create a new HDL file with the New Design Wizard and how to utilize the HDE features within that created source file.

3.1 Compilation and Simulation: Compilation and Simulation

Learn how to specify design settings for compilation (setting up debugging windows, selecting maximum optimization, etc.), how to initialize and run simulations, how to view the simulation results, and how to perform compilation and simulation with scripts.

3.2 Compilation and Simulation: Compiling Vivado Simulation Libraries

When you instantiate any Xilinx black box component in your design, Active-HDL will look for the vendor libraries to define functionality of the Xilinx Component. Before performing simulation of these designs, it is crucial not only to have the proper simulation libraries, but the correct version as well.

3.3 Compilation and Simulation: Running Active-HDL in Batch Mode Using vSimSA

This video will cover how to access both Interactive Mode and Batch Mode as well as demonstrating some basic commands in the VSimSA shell and OS shell to set libraries, compile files, and run simulation.

4.1 Debugging: Introduction to Debugging

In this video we will look at console window, breakpoints, watch window, process window, call stack window, waveform and list viewer briefly among the vast debugging tools that exist on Active HDL.

4.2 Debugging: Advance Dataflow

Learn how to enable settings to generate data for the Advanced Dataflow window, how to add/view modules in the Advanced Dataflow window, how to utilize context menus within the window (expand net to readers, expand net to drivers, etc.), and how to switch display modes.

4.3 Debugging: X-trace

This tool can also be used with the Advanced Dataflow debugging tool. Learn how to enable XTrace, set XTrace options, and view signals that contain unknown values.

4.4 Debugging: Waveform Viewer

This video will demonstrate accessing the Waveform Viewer and the tool’s advanced features such as bookmarks, grouping signals, aliases, and altering signal properties.

4.5 Debugging: Assertions Viewer

This video provides an overview on how to access and use the Assertion Viewer window.

5.1 Coverage: Code Coverage

This video will demonstrate how to access Code Coverage and view the results in Active HDL’s coverage database through acdb or html format.

5.2 Coverage: FSM Coverage

Active-HDL provides a number of coverage analysis tools to further enhance verification quality of HDL code. Coverage analysis uses ACDB (Aldec Coverage Database) as a unified format of storing different types of coverage data.

5.3 Coverage: Toggle Coverage

This video will demonstrate how to enable Toggle Coverage, how to generate Toggle Coverage report, and how to read Toggle Coverage data.

6.1 Tools: Traceability

Learn how to access Spec-TRACER, configure Spec-TRACER settings, and generate and understand the Spec-TRACER traceability reports.

6.2 Tools: Code2Graphics

This video will show how to use Code2Graphics™ to create block diagrams and state diagrams.

7.1 Customization & Integration: User-defined Design Management

Learn how to customize the design structure, edit/copy/share the design structure configuration file, and convert existing designs to the new structure.

7.2 Customization & Integration: Vivado TCL store Integration

In this video, you will learn how to integrate Active-HDL’s simulator into the Vivado workflow.

7.3 Customization & Integration: Unit Linting

Active-HDL offers the design rule checking capabilities of ALINT-PRO directly within the tool through unit linting.

7.4 Customization & Integration: Simulation & Debugging with Intel Quartus Prime Pro

This video provides a general overview of how to simulate and debug with Active-HDL through Quartus Prime Pro using one of Quartus’ sample IP designs.

7.5 Customization and Integration: Simulation and Debugging with Xilinx Vivado

This video provides a general overview of how to simulate and debug Vivado projects using Active-HDL's simulator environment.

7.6 Customization & Integration: Simulation & Debugging with Microchip Libero SoC

This video provides a general overview of how to simulate and debug Libero projects using Active-HDL™s simulator environment.

8.1 License Installation Aldec Products (Nodelock and Floating)

This video will cover how to determine the license type as well as how to properly install each type of license onto a Windows machine.