ASIC/FPGA High Level Synthesis Solution from NEC

Aldec (tried to) quietly introduce our new friends from NEC Japan for the first time at DAC this year. They joined us in our booth in Austin and were soon the life of the party as many people were eager to learn about CyberWorkbench’s C-based integrated environment.

Aldec now has a distributor agreement in place with NEC, so we can proudly announce today that CyberWorkBench®, NEC’s well-established High Level Synthesis solution, is now featured in Aldec’s verification ecosystem. Here’s an excerpt from today’s press release:

“Aldec has been a trusted name in the EDA industry for 30 years. Combining high level synthesis technology from NEC with Aldec’s verification ecosystem provides designers a full solution for SoC design and validation.” said Kazutoshi Wakabayashi, Senior Expert, Embedded System Solutions Business Center and Green Platform Research Laboratories, NEC.

While traditional hardware design involves RTL development and debugging, the increase in the complexity of today’s designs render the traditional approach too time consuming and error prone. Where the entire focus of designing hardware is shifted from traditional RTL method to a higher abstraction level, development time and cost savings can be significant.

You can view the rest of this press release in the Aldec Newsroom.

For more on CyberWorkBench, visit www.aldec.com/products/cyberworkbench or check out these resources:

Upcoming Webinar: CyberWorkBench: C-based High Level Synthesis and Verification – Sept. 12