Company Newsroom Industry’s First use of TLM for the At-Speed Verification of a PCIe-Based Avionics Design Requiring DO-254 Compliance Release Feb 14, 2022 Productivity Through Methodology: Aldec Adds UVM Generator to Riviera-PRO™ Plus Updates Its OSVVM and UVVM Libraries Release Nov 16, 2021 New HES Board is Ideal for Prototyping and Emulating Medium to Large ASIC & SoC Designs Release Aug 16, 2021 New TySOM-M Series Targets Low Power, High Security Applications Release Jul 7, 2021 Aldec Launches HES-DVM Proto ‘Cloud Edition’ - Giving Engineers Easier Access to FPGA-based ASIC & SoC Prototyping Release Jun 2, 2021 Airborne System Design Assurance: Aldec Adds 60+ New HDL Rules to ALINT-PRO’s DO-254 Plug-In Release Mar 4, 2021 Powerful FPGA Design Creation and Simulation IDE Adds VHDL-2019 Support & OSVVM Enhancements Release Jan 20, 2021 RECENT NEWS What’s involved in simulation of a complex SoC FPGA like Versal ACAP?In the News FEB 08, 2024Aldec @ DAC 2023: Presenting Design Verification Tools and Solutions for FPGAs and SoCsRelease JUN 26, 2023Riviera-PRO Supports System Simulation of AMD® Versal™ ACAP DesignsRelease JUN 14, 2023The avionics industry’s growing need for TLMIn the News MAY 18, 2023Aldec and Thales to Co-Present at Certification Together International Conference 2023Release MAY 01, 2023Aldec Releases Automated Static Linting and CDC Analysis for Microchip FPGA and SoC FPGA DesignsRelease FEB 06, 2023 view all news RECENT YOUTUBE VIDEOS VHDL 2019 Just the New Stuff Part 1: Interfaces, Conditional Analysis, File IO, & New Environment HW/SW Co-simulation solution for Zynq SoC based systems using Riviera-PRO and QEMU Riviera PRO Product Overview How to Connect Partition's Logical Connections on Multi-FPGA Prototyping Board Using HES-DVM on AWS view all videos RECENT BLOG ARTICLES Scalable Cloud-based CI/CD HDL Verification Environment Enhance Your Verification Workflow with Azure, VUnit, and Riviera-PRO Navigating VUnit: A Practical Guide to Modifying Testing Approaches Speeding Up Simulation with VUnit for Parallel Testing Introduction to VUnit FPGA Design Verification in a Nutshell view all articles UPCOMING EVENTS Using SVA for Requirements-Based Verification of Safety-Critical FPGA Designs Webinar JUL 23, 2025Hierarchical approach analysis using ALINT-PROWebinar JUL 30, 2025HDLRegression – Automated Regression Testing for VHDL/Verilog (US)Webinar AUG 21, 2025HDLRegression – Automated Regression Testing for VHDL/Verilog (EU)Webinar AUG 21, 2025 view all events
