Company Newsroom New HES Board is Ideal for Prototyping and Emulating Medium to Large ASIC & SoC Designs Release Aug 16, 2021 New TySOM-M Series Targets Low Power, High Security Applications Release Jul 7, 2021 Aldec Launches HES-DVM Proto ‘Cloud Edition’ - Giving Engineers Easier Access to FPGA-based ASIC & SoC Prototyping Release Jun 2, 2021 Riviera-PRO™: Enables VHDL-2019 Users to Unleash the Power of the Language’s New Additions Release May 18, 2021 Airborne System Design Assurance: Aldec Adds 60+ New HDL Rules to ALINT-PRO’s DO-254 Plug-In Release Mar 4, 2021 Powerful FPGA Design Creation and Simulation IDE Adds VHDL-2019 Support & OSVVM Enhancements Release Jan 20, 2021 RECENT NEWS New HES Board is Ideal for Prototyping and Emulating Medium to Large ASIC & SoC DesignsRelease JUL 19, 2021New TySOM-M Series Targets Low Power, High Security ApplicationsRelease JUL 07, 2021Aldec Launches HES-DVM Proto ‘Cloud Edition’ - Giving Engineers Easier Access to FPGA-based ASIC & SoC PrototypingRelease JUN 02, 2021Riviera-PRO™ Enables VHDL-2019 Users to Unleash the Power of the Language’s New AdditionsRelease MAY 18, 2021Airborne System Design Assurance: Aldec Adds 60+ New HDL Rules to ALINT-PRO’s DO-254 Plug-InRelease MAR 04, 2021Powerful FPGA Design Creation and Simulation IDE Adds VHDL-2019 Support & OSVVM EnhancementsRelease JAN 20, 2021 view all news RECENT YOUTUBE VIDEOS How to Connect Partition's Logical Connections on Multi-FPGA Prototyping Board Using HES-DVM on AWS How to Run User Guided Multi FPGA Partitioning Using Aldec's HES-DVM on the AWS Cloud How to Prepare HES DVM Compatible Custom Board Files Using Board Compiler Tool How to Automatically Partition an ASIC Design into Multiple FPGAs Using HES DVM view all videos RECENT BLOG ARTICLES Development of real-time SDR systems with Aldec HES Performing cross spectrum video processing on a TySOM-3 board Matching image data between the thermal and visible spectrum for non-contact human body temperature screening helps in the fight against COVID-19 How does the Mars Perseverance rover benefit from FPGAs as the main processing units? FPGAs on Mars SynthHESer - Aldec’s New Synthesis Tool Linting RISC-V designs with ALINT-PRO view all articles UPCOMING EVENTS Using OVL for Assertion-Based Verification of Verilog and VHDL Designs (EU)Webinar OCT 21, 2021Using OVL for Assertion-Based Verification of Verilog and VHDL Designs (US)Webinar OCT 21, 2021Constraint Random Verification with Python and Cocotb (EU)Webinar NOV 04, 2021Constraint Random Verification with Python and Cocotb (US)Webinar NOV 04, 2021 view all events
