Company Newsroom Aldec’s TySOM Embedded Development Kits are Now Qualified for AWS IoT Greengrass Release Aug 5, 2020 Aldec Provides Static Verification for RISC-V Designs with the latest release of ALINT-PRO Release Jul 22, 2020 Faster FPGA Verification Release Jun 22, 2020 New to Riviera-PRO™: VHDL-2019 Support and a Versatile UVM Registers Window Release Jun 24, 2020 Aldec Adds Customizable Tool Qualification Data Package to ALINT-PRO™ for DO-254 Projects Release Jun 30, 2020 RECENT NEWS Aldec’s TySOM Embedded Development Kits are Now Qualified for AWS IoT Greengrass Release AUG 05, 2020Aldec Provides Static Verification for RISC-V Designs with the latest release of ALINT-PRORelease JUL 22, 2020Aldec @ DAC 2020: Presenting RISC-V Verification Methodologies and SolutionsRelease JUL 15, 2020Aldec Adds Customizable Tool Qualification Data Package to ALINT-PRO™ for DO-254 ProjectsRelease JUN 30, 2020New to Riviera-PRO™: VHDL-2019 Support and a Versatile UVM Registers WindowRelease JUN 24, 2020Faster FPGA verificationIn the News JUN 22, 2020 view all news RECENT YOUTUBE VIDEOS PCIe 5 Simulation Verification Demonstration Unboxing TySOM-3A-ZU19EG Embedded Development Board DAC 2019 Demo - Hybrid Co Emulation with ARM Hardware Model DAC 2019 Demo - SoC Simulation Environment for Mixed Signal Designs view all videos RECENT BLOG ARTICLES SynthHESer - Aldec’s New Synthesis Tool Linting RISC-V designs with ALINT-PRO Enabling TySOM Zynq-based Embedded Development Board for AWS IoT Greengrass Qualified Zynq SoC Dev Board for IoT Greengrass Connecting Emulated Design to External PCI Express Device Is your Verification plan pulling you in multiple directions? Try FSM Coverage A quick look into FSM Coverage view all articles UPCOMING EVENTS Static Verification for RISC-V Cores and SoCs (US)Webinar OCT 01, 2020Static Verification for RISC-V Cores and SoCs (EU)Webinar OCT 01, 2020DVCon EU 2020Industry Event OCT 27, 2020 view all events
