Company Newsroom Aldec’s TySOM Family of Embedded System Development Solutions Now Supports Xilinx PYNQ (Python Productivity for Zynq) Release Oct 21, 2020 Aldec Provides Static Verification for RISC-V Designs with the latest release of ALINT-PRO Release Jul 22, 2020 Aldec Introduces Hardware Assisted RTL Simulation Acceleration for Microchip FPGA Designs Release Nov 3, 2020 New to Riviera-PRO™: VHDL-2019 Support and a Versatile UVM Registers Window Release Jun 24, 2020 Aldec Adds Customizable Tool Qualification Data Package to ALINT-PRO™ for DO-254 Projects Release Jun 30, 2020 RECENT NEWS Airborne System Design Assurance: Aldec Adds 60+ New HDL Rules to ALINT-PRO’s DO-254 Plug-InRelease MAR 04, 2021Powerful FPGA Design Creation and Simulation IDE Adds VHDL-2019 Support & OSVVM EnhancementsRelease JAN 20, 2021Riviera-PRO™: OSVVM 2020.08 inclusion, enhanced language support, and new debugging features aim to boost productivityRelease DEC 08, 2020SemiWiki: Aldec Adds Simulation Acceleration for Microchip FPGAsIn the News NOV 10, 2020Aldec Introduces Hardware Assisted RTL Simulation Acceleration for Microchip FPGA DesignsRelease NOV 03, 2020Aldec’s TySOM Family of Embedded System Development Solutions Now Supports Xilinx PYNQ (Python Productivity for Zynq) Release OCT 21, 2020 view all news RECENT YOUTUBE VIDEOS ALDEC DEMO - HDL Linting for RISC V Cores ALDEC DEMO - RISC V Design and Verification with FPGA Hardware In The Loop ALDEC DEMO - UVM Based Environment for Ibex RISC V CPU Core with Google RISC V DV ALDEC DEMO - Integrated UVM Environment for Verifying Adding Custom Instructions to RISC V Cores view all videos RECENT BLOG ARTICLES Performing cross spectrum video processing on a TySOM-3 board Matching image data between the thermal and visible spectrum for non-contact human body temperature screening helps in the fight against COVID-19 How does the Mars Perseverance rover benefit from FPGAs as the main processing units? FPGAs on Mars SynthHESer - Aldec’s New Synthesis Tool Linting RISC-V designs with ALINT-PRO Enabling TySOM Zynq-based Embedded Development Board for AWS IoT Greengrass Qualified Zynq SoC Dev Board for IoT Greengrass view all articles UPCOMING EVENTS VHDL-2019: Just the New Stuff Part 1: Interfaces, Conditional Analysis, File IO, and The New Environment (EU)Webinar APR 22, 2021VHDL-2019: Just the New Stuff Part 1: Interfaces, Conditional Analysis, File IO, and The New Environment (US)Webinar APR 22, 2021VHDL-2019: Just the New Stuff Part 2: Protected Types and Verification Data Structures (US)Webinar MAY 06, 2021VHDL-2019: Just the New Stuff Part 2: Protected Types and Verification Data Structures (EU)Webinar MAY 06, 2021 view all events
