Company Newsroom Industry’s First use of TLM for the At-Speed Verification of a PCIe-Based Avionics Design Requiring DO-254 Compliance Release Feb 14, 2022 Productivity Through Methodology: Aldec Adds UVM Generator to Riviera-PRO™ Plus Updates Its OSVVM and UVVM Libraries Release Nov 16, 2021 New HES Board is Ideal for Prototyping and Emulating Medium to Large ASIC & SoC Designs Release Aug 16, 2021 New TySOM-M Series Targets Low Power, High Security Applications Release Jul 7, 2021 Aldec Launches HES-DVM Proto ‘Cloud Edition’ - Giving Engineers Easier Access to FPGA-based ASIC & SoC Prototyping Release Jun 2, 2021 Airborne System Design Assurance: Aldec Adds 60+ New HDL Rules to ALINT-PRO’s DO-254 Plug-In Release Mar 4, 2021 Powerful FPGA Design Creation and Simulation IDE Adds VHDL-2019 Support & OSVVM Enhancements Release Jan 20, 2021 RECENT NEWS Advancing VHDL’s Verification Capabilities with VHDL-2019 Protected TypesRelease MAR 29, 2022Aldec Suspends all EDA Sales and Distribution Transactions in RussiaRelease MAR 14, 2022Industry’s First use of TLM for the At-Speed Verification of a PCIe-Based Avionics Design Requiring DO-254 ComplianceIn the News JAN 13, 2022Productivity Through Methodology: Aldec Adds UVM Generator to Riviera-PRO™ Plus Updates Its OSVVM and UVVM Libraries Release NOV 16, 2021New HES Board is Ideal for Prototyping and Emulating Medium to Large ASIC & SoC DesignsRelease JUL 19, 2021New TySOM-M Series Targets Low Power, High Security ApplicationsRelease JUL 07, 2021 view all news RECENT YOUTUBE VIDEOS How to Connect Partition's Logical Connections on Multi-FPGA Prototyping Board Using HES-DVM on AWS How to Run User Guided Multi FPGA Partitioning Using Aldec's HES-DVM on the AWS Cloud How to Prepare HES DVM Compatible Custom Board Files Using Board Compiler Tool How to Automatically Partition an ASIC Design into Multiple FPGAs Using HES DVM view all videos RECENT BLOG ARTICLES The Convergence of Emulation and Prototyping Development of real-time SDR systems with Aldec HES Performing cross spectrum video processing on a TySOM-3 board Matching image data between the thermal and visible spectrum for non-contact human body temperature screening helps in the fight against COVID-19 How does the Mars Perseverance rover benefit from FPGAs as the main processing units? FPGAs on Mars SynthHESer - Aldec’s New Synthesis Tool view all articles UPCOMING EVENTS Better FPGA Verification with VHDLPart 1: OSVVM - Leading Edge Verification for the VHDL Community (US)Webinar MAY 26, 2022Better FPGA Verification with VHDLPart 1: OSVVM - Leading Edge Verification for the VHDL Community (EU)Webinar MAY 26, 2022Better FPGA Verification with VHDLPart 2: Faster than "Lite" Verification Component Development with OSVVM (US)Webinar JUN 09, 2022Better FPGA Verification with VHDLPart 2: Faster than "Lite" Verification Component Development with OSVVM (EU)Webinar JUN 09, 2022 view all events
