...
...
Company Newsroom
Recent News
Aldec Provides the Industry’s Most-Comprehensive Portfolio of FMC Daughter Cards Release NOV 14, 2019 Aldec at DVCon Europe: Demonstrating a hybrid co-verification platform for ASIC/SoC projects and automated FPGA partitioning software Release OCT 21, 2019 Aldec’s Focus for Arm TechCon is on Deep Neural Network and Machine Learning Application Development Release OCT 02, 2019 Aldec cuts ASIC design prototype bring-up time with HES-DVM’s automatic partitioning tool and faster HDL-to-FPGA compilation times Release SEP 24, 2019 SoC & ASIC designers to benefit greatly from multiple HES Proto-AXI™ enhancements Release SEP 09, 2019 Riviera-PRO™ users to benefit from automatic UVM register generation plus the latest verification methodology libraries Release JUN 18, 2019 Introducing SyntHESer, Aldec’s proprietary high-speed synthesizer for HES emulation and prototyping Release JUN 03, 2019 Aldec @ DAC 2019: Celebrating its 35th Anniversary and focusing on design acceleration, co-verification and mixed-signal Release MAY 15, 2019 Hardware Lifecycle Data Management for Teams Release APR 01, 2019 Latest TySOM Kit Accelerates the Development of AI, DNN and Other Algorithm Acceleration-dependent Applications Plus Aids SoC Prototyping Release FEB 26, 2019Recent Blog Articles
SoC Verification Never Been Easier
Bird’s eye view definition, HW/SW setup and implementation algorithms
Aldec’s Co-Simulation Solution using QEMU and Riviera-PRO
Upcoming Events
Industry Event Denver, CO NOV 18, 2019