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Company Newsroom
Recent News
Riviera-PRO™ users to benefit from automatic UVM register generation plus the latest verification methodology libraries Release JUN 18, 2019 Introducing SyntHESer, Aldec’s proprietary high-speed synthesizer for HES emulation and prototyping Release JUN 03, 2019 Aldec @ DAC 2019: Celebrating its 35th Anniversary and focusing on design acceleration, co-verification and mixed-signal Release MAY 15, 2019 Hardware Lifecycle Data Management for Teams Release APR 01, 2019 Latest TySOM Kit Accelerates the Development of AI, DNN and Other Algorithm Acceleration-dependent Applications Plus Aids SoC Prototyping Release FEB 26, 2019 Aldec facilitates design prototyping in FPGA and prototype testing with new HES Proto-AXI Release JAN 22, 2019 Aldec shortens time of ASIC design prototype bring-up in FPGA with HES-DVM Proto mode Release JAN 14, 2019 VHDL 2018 Support & Enhanced Automation - Aldec adds VHDL Standard 1076-2018 extensions and automatic coverage model generation to Riviera-PRO™ Release NOV 13, 2018 Aldec’s “Hardware and Software Co-verification in Hybrid Simulation and Emulation Environment with QEMU” DVCon Europe tutorial to demonstrate how engineers can obtain a holistic view over their SoC design Release OCT 22, 2018 A View from Above Release OCT 15, 2018Recent Blog Articles
Bird’s eye view definition, HW/SW setup and implementation algorithms
Aldec’s Co-Simulation Solution using QEMU and Riviera-PRO
Understanding High speed serial data transfer