Camouflage for Your HDL Code Mariusz Grabowski, FPGA Design and Verification Engineer Like(1) Comments (0) Designers may deliberately obfuscate HDL code to conceal its purpose (security through obscurity) or its logic, in order to prevent tampering and deter reverse engineering. The obfuscated code is unreadable to the receiving user, but is still readable to compilers and simulators. This way obfuscation also comes in handy when you need to share your source code with an EDA tool vendor for debugging and don't want the recipient to see the contents of the actual file. Aldec provides the script to obfuscate VHDL, Verilog, and SystemVerilog code. For steps to execute this script, see related App Note, HDL Code Obfuscation. Tags:VHDL,Verilog,SystemVerilog,Functional Verification
