Aldec Design and Verification Blog

Trending Articles
Speeding Up Simulation with VUnit for Parallel Testing

Effective simulation is essential in hardware development, as time and accuracy are critical factors that can determine the success or failure of a project....

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Versal ACAP Simulation Challenges

The electronics industry is all about optimization, and always has been. For example, you might think of system on chip (SoC) as a relatively recent term, coined this century. However, many regard the silicon that appeared in digital watches in the 1970s as constituting a system on a chip, ...

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SynthHESer - Aldec’s New Synthesis Tool

In the early days of digital design, all circuits were designed manually. You would draw K-map, optimize the logic and draw the schematics. If you remember, we all did many logic optimization exercises back in college....

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Linting RISC-V designs with ALINT-PRO

As the open-source RISC-V instruction set architecture (ISA) continues to gain momentum, the growing number of RISC-V design solutions, and their flexibility, creates a problem when choosing the most reliable and robust solution from a number of contenders....

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Is your Verification plan pulling you in multiple directions? Try FSM Coverage
A quick look into FSM Coverage

The verification process is long and time consuming, especially when you are not sure what you are looking for. There are a lots of directions you can go looking for bugs but without a guide, without a plan you will most likely be going in circles....

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Problems Accessing Registers? – See how UVM RAL can help

As a digital design or verification engineer you know that certain features or configurations of the device can be achieved by programming some registers to set values.For example, a 32-bit register can have several fields within it...

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Verification Effectiveness with Riviera-PRO: SystemVerilog Randomized Layered Testbench
Understanding SystemVerilog Layered Testbench

In this blog, I will discuss randomized layered testbenches used in SystemVerilog. We need to understand why we need it,...

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SystemVerilog Functional Coverage in a Nutshell
Use native SystemVerilog constructs as metrics for verification closure in Riviera-PRO

Let’s say you have a block you need to verify. How do you know that the stimulus you are about to use is exhaustive enough and that you have covered the necessary scenarios/situations to prove it is working correctly?...

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Trace Your Assertions

When I enter the word “assertions” into a search engine I get lots of results, including articles, books, courses, and tools. Nothing unusual there, as assertions have been present in the EDA industry for many years. They considerably increase...

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Acceleration-Ready UVM
Guest Blog by Doulos CTO, John Aynsley

We hear that emulation is one of the fastest-growing segments in EDA right now, yet simulation still continues to be the main workhorse for functional verification, and SystemVerilog and UVM are everywhere you look....

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