Aldec Design and Verification Blog Trending Articles FPGA Design Verification in a Nutshell Versal ACAP Simulation Challenges Real-time SDR system with TySOM The Convergence of Emulation and Prototyping Development of real-time SDR systems with Aldec HES Performing cross spectrum video processing on a TySOM-3 board How does the Mars Perseverance rover benefit from FPGAs as the main processing units? All Categories Corporate DO-254 Compliance Embedded Solutions Emulation/Acceleration FPGA Design Functional Verification High Performance Computing Requirements Management SoC and ASIC Prototyping SoC Design and Validation Specialized Applications FPGA Design Verification in a Nutshell FPGA Design Verification (Planning) in a Nutshell Before wading into this topic, I’d like to state why I felt compelled to write about FPGA design verification. I recently presented a very well attended three-part webinar series, during which many attendees asked for book recommendations.... Tags:ASIC,Coverage,Design,Functional Verification,Debugging,Documentation,Digital,SoC,Verification,Verilog,VHDL Like(0) Comments (0) Read more Versal ACAP Simulation Challenges The electronics industry is all about optimization, and always has been. For example, you might think of system on chip (SoC) as a relatively recent term, coined this century. However, many regard the silicon that appeared in digital watches in the 1970s as constituting a system on a chip, ... Tags:Embedded,FPGA,Riviera-PRO,FPGA Simulation,Functional Verification,safety-critical,SystemC,SystemVerilog,VHDL,UVM Like(0) Comments (0) Read more Is your Verification plan pulling you in multiple directions? Try FSM Coverage A quick look into FSM Coverage The verification process is long and time consuming, especially when you are not sure what you are looking for. There are a lots of directions you can go looking for bugs but without a guide, without a plan you will most likely be going in circles.... Tags:Coverage,Debugging,Design,FPGA,SystemVerilog,Verilog,VHDL Like(1) Comments (8) Read more HW/SW Co-Simulation for SoC FPGA designs Aldec’s Co-Simulation Solution using QEMU and Riviera-PRO Heterogeneous System on Chip (SoC) devices like the Xilinx Zynq 7000 and Zynq UltraScale+ MPSoC combine a high-performance processing system (PS) with state-of-the-art programmable logic (PL).... Tags:Co-simulation,Embedded,FPGA,Hardware,HDL,Simulation,SoC,Validation,Verification,Verilog,VHDL,Xilinx Like(2) Comments (0) Read more The Race to Zero Latency for High Frequency Trading The High-Frequency Trading (HFT) industry has received a lot of attention during the last few years. HFT is all about speed and minimizing latency: the faster you can run trading strategies and algorithms for analyzing minute price changes... Tags:Aceleration,Coverage,Verification,Verilog,VHDL Like(2) Comments (0) Read more FPGA vs GPU for Machine Learning Applications: Which one is better? Can FPGAs beat GPUs? FPGAs or GPUs, that is the question. Since the popularity of using machine learning algorithms to extract and process the information from raw data, it has been a race between FPGA and GPU vendors to offer... Tags:Aceleration,Embedded,FPGA,Hardware,HDL,Validation,Verilog,VHDL,Xilinx Like(3) Comments (0) Read more How to develop an FPGA-based Embedded Vision application for ADAS, series of blogs – Part 1 FPGA “The winner for the low-power and high-performance vision-based applications” When should we use the term “Vision for Everything”, as vision-based applications are entering various industries? It’s been a few years since the emergence of... Tags:Aceleration,ARM,Embedded,FPGA,Hardware,Verilog,VHDL,Xilinx Like(2) Comments (0) Read more Code Coverage in HDL Editor? Now That’s a Nice Feature. For a long time I have been a fan of code coverage tools that are embedded into the simulators themselves, and which give you the ability to switch easily between the code and the coverage results. It is particularly helpful to have a way... Tags:Verification,Verilog,VHDL,Coverage Like(1) Comments (0) Read more VHDL-2017: Some of My Favorite Things For the past several years I have had the privilege to chair the IEEE 1076 VHDL working group. In March we handed off the revisions to the VHDL LRM to our technical editor to finalize the document for balloting. As we are waiting for the standards process to finish up, I thought I would share my favorite new additions. Let me start with an executive summary: ... Tags:HDL,IEEE,Simulation,Verification,VHDL Like(4) Comments (0) Read more FPGA VHDL Verification How can we do this faster and with better quality - at no extra cost? This is actually possible – and with an average efficiency improvement of 20 to 50% for medium to high complexity FPGAs. Less for data path oriented designs and more for control or protocol oriented designs. At no extra cost.... Tags:Debugging,VHDL Like(4) Comments (0) Read more
