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Date Event Type Location Action
Oct 13, 2022 Assertions-Based Verification for VHDL Designs (EU)

Time: 3:00 PM - 4:00 PM (CEST)



Assertion-based verification (ABV) enables the use of assertions for the efficient verification of low-level design properties. These assertions could be verified by simulation and formal verification methods. The VHDL 2008 standard includes Property Specification language (PSL) to express design properties for both simulation and static formal analysis. For mixed-mode simulations of VHDL designs with SystemVerilog testbenches, SystemVerilog Assertions (SVA) standard provides means to express both immediate and concurrent assertions as well as functional coverage constructs.


In this webinar, we will present various methods to implement assertions in VHDL designs as well as identify the strengths and limitations of each method. These methods include PSL (VHDL flavor), the usage of Open Verification Library (OVL) as well as concurrent assertions development using procedural code with assert statements.



  • Assertion Based Verification Overview
  • Developing Assertions in VHDL PSL, assert statement
  • OVL VHDL for assertions specification
  • Binding SVA with VHDL designs
  • Assertion-based Verification Design Example
  • Conclusion
  • Q&A


Presenter BIO

Alexander Gnusin, Design Verification Technologist.
Alex accumulated 27 years of hands-on experience in various aspects of ASIC and FPGA design and verification. As a verification prime for a multi-million gates project in companies such as IBM, Nortel, Ericsson and Synopsys Inc, he combined various verification methods such as static linting, formal property checking, dynamic simulation and hardware-assisted acceleration to efficiently achieve design verification goals. He received his M.S. in Electronics from Technion, Israel Institute of Technology.

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